LCD Display Driver Circuit



 Fig.  shows the  circuit  for  driving  LCD  seven  segment  y  using  IC  4543B.The 4543B BCD-to-7 segment latch/decoder/driver is  designed for liquid crystal Pins A,
B,  C  and  D  represent  BCD inputs  with  A as  a least  significant  bit  (LSB)  as  a most significant bit (MSB). Pins a through g are the seven segment outputs. It has three
control terminals LD (Latch Disable), PH (Phase), and BL (Blank). In internal use the
LD  terminal  is  held  high  and  BL  terminal  is  tied  low.  The  state  of  the  PH  terminal depends on the type of display that is being driven. For driving LCD displays, square
wave (about 60Hz swinging fully between the GND and Vcc values) must b applied to
the phase terminal.




The display can be blanked by simply driving the BL terminal to the logic high state. When the LD terminal is in its normal high state, BCD inputs are decoded and fed directly to the seven segment output terminals of the IC. When the LD terminal    is pulled low, the BCD input signals that are present at the moment of transition are latched into memory and fed to the seven segment outputs.

The Fig shows how above circuit can be used to drive a 4-digit  nonmultiplexed, 7-segment LCD display. Here, BCD input for each display is latched  in the corresponding latch. The latch enable signals are activated using 2: 4 decoder in synchronization with the BCD inputs.











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