WHAT HAPPENS WHEN AN INTERRUPT ENDS?

An interrupt ends when the program executes the RETI (Return from Interrupt) instruction. 

When the RETI instruction is executed the following actions are taken by the microcontroller:

•    Two bytes are popped off the stack into the Program Counter to restore normal program execution.

•    Interrupt status is restored to its pre-interrupt status.

8085 Microprocessor Based DC Motor Speed Control System

•    Varying  the  armature  voltage  varies  the  speed  of  the  dc  motor  and  e  field  voltage  is  kept
constant.  A  controlled  rectifier  using  SCR  develops  the  required  armature  voltage  and  the uncontrolled rectifier generates the required field voltage.

•    The microprocessor controls the speed of the motor by varying the firing angle of SCRs in the controlled rectifier.

•    The system has EPROM for system program storage, and RAM for  temporary data storage and stack.

•    A keyboard has been provided to input the desired speed and other commands to operate the system.

•    In order to display the speed of the  motor, 7-segment LED display has been provided. The keyboard  and  7-segment  LED  display  has  been  interfaced  to  8085  based  system  using Keyboard display controller INTEL 8279.

8085 Microprocessor based dc motor speed control system

 
•    The speed of the dc motor is measured using a tachogenerator. It produces an analog voltage proportional to the speed of the motor.

•    Then  the  analog  signal  is  scaled  to  desired  level  by  the  signal  conditioning  circuit  and digitized  using  ADC.  (The  processor  cannot  process  the  analog  signal  directly,  hence  the analog signal is digitized using ADC).

•    The  ADC  is  interlaced  to  8085  processor  through  the  port-B  and  port-C  of  8255.  The processor  can  send  a  start  of  conversion  to  ADC  through  port-C  pin  and  at  the  end  of conversion it can read the digital data from port-B of 8255. This digital data is proportional to actual speed.

•    The processor calculates the actual speed and displays it on LEDs.

•    Also,  the  processor  compares  the  actual  speed  with  desired  speed  entered  by  the  operator through the keyboard. If there  is  a  difference  then the  error  is estimated.  The error  can  be modified  by  a  digital  control  algorithm,  (P/PI/PID/FUZZY  logic  control  algorithm)  to produce a digital control signal.

•    The digital control signal is converted to analog signal by the DAC. The analog signal is used
to alter the firing angle of SCRS in the controlled rectifiers. The operational the speed control system is shown in the following flowchart.

Flow chart for DC motor speed control system

APPLICATIONS OF 8085 MICROPROCESSOR (DAC INTERFACE)

DAC  INTERFACE 

In many applications, the microprocessor has to produce analog signals for controlling certain analog devices. Basically the microprocessor system can produce only digital signals. In order to convert the digital signal to analog signal a Digital-to-Analog Converter. (DAC) has to be employed.

The DAC will accept a digital (binary) input and convert to analog voltage or current. Every DAC will have "n" input lines and an analog output.

The DAC require a reference analog voltage (Vref) or current (Iref) source.

The smallest possible analog value that can be represented by the n-bit binary code is called resolution. The resolution of DAC with n-bit binary input is 1/2n of reference analog value. Every analog output will be a multiple of the resolution. In some converters the input reference analog signal will be multiplied or divided by a constant to get full scale value. Now the resolution will be 1/2n of full scale value.

For example,
Consider an 8-bit DAC with reference analog voltage of 5 volts.
Now the resolution of the DAC is (1/28) x 5 volts.
The 8-bit digital input can take, 28 = 256 different values.
The analog values for all possible digital input are as shown in table below.

The maximum input digital signal will have an analog value which is equal to reference analog value minus resolution.

The digital-to-analog converters can be broadly classified into three categories, and they are

•    Current output
•    Voltage output 
•    Multiplying type

The current output DAC provides an analog current as output signal.
In voltage output DAC, the analog current signal is internally converted to voltage signal.

In multiplying type DAC, the output is given by the product of the input signal and the reference source and the product is linear over a broad range. Basically, there is not much difference between these three types and any DAC can be viewed as multiplying DAC.

Typical DAC circuit:

The basic components of a DAC are resistive network with appropriate values, switches, a reference source and a current to voltage converter as shown in figure below.

The switches in the circuit of figure above can be transistors which connects the resistance either to ground or Vref.  The resistors are connected in such a way that for any number of inputs, the total current is in binary proportion. The operational amplifier converts the current to a voltage signal V0, which can be calculated from the following equation. 

The circuit of figure shown above can be modified as 8-bitDAC, by increasing the number of R/2R ladder. For an 8-bit DAC the output voltage is given by

The time required for converting the digital signal to analog signal is called conversion time. It depends on the response time of the switching transistors and the output amplifier. If the DAC is interfaced to microprocessor then the digital data (Signal) should remain at the input of DAC, until the conversion is complete. Hence to hold the data a latch is provided at the input of DAC. 

The Digital-to-Analog converters compatible to microprocessors are available with or without internal latch and I to V converting amplifier. The AD558 of Analog Devices is an example of 8-bit DAC with an internal latch and I to V converting amplifiers. The output of AD558 is an analog voltage signal.     The AD558 can be directly interfaced to 8085 microprocessor bus and it requires only two control signals: Chip Select (CS) and Chip Enable (CE). [No handshake signals are necessary for interfacing a DAC. The time between loading two digital data to DAC is controlled by software time delay].

The DAC0808 of National Semiconductor Corporation is an example of 8-bit DAC without internal latch and I to V converting amplifier. The internal block diagram and the pin configuration of DAC0808 are shown in figure below.

The DAC0800 can be interfaced to 8085 system through an 8-bit latch as shown in figure below. The chip select (CS) signal from the decoder of the microprocessor system is delayed and inverted to clock the latch. If the DAC is memory mapped then the CS is from memory decoder. If the DAC is I/O mapped then CS is from I/O decoder. 

 

The processor sends an address, which is decoded by decoder in the microprocessor system to produce chip select signal. Then the processor sends a digital data to latch. The buffer and inverter will produce sufficient delay for CS signal so that, the latch is clocked only after the data is arrived at the input lines of the latch. When the latch is clocked the digital data is send to DAC. The DAC will produce a corresponding current signal, which is converted to voltage signal by the op-amp 741. The typical settling time of DAC0800 is 150nsec. Therefore the processor need not wait for loading next data.

INTERFACING 8259 WITH 8085 MICROPROCESSOR:

•    It requires two internal address and they are A =0 or A = 1.

•    It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085 is shown in figure is I/O mapped in the system.

•    The low order data bus lines D0-D7 are connected to D0-D7 of 8259.

•    The  address  line  A0  of the  8085  processor  is  connected  to  A0   of  8259  to  provide  the  internal address.

•    The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for
8259.

•    The address lines A4, A5  and A6  are used as input to decoder.

•    The control signal IO/M (low) is used as logic high enables for decoder and the address line A7  is used as logic low enable for decoder.

•    The I/O ad4ressès of 8259 are shown in table-8.5.

Working of 8259 with 8085 processor:

•    First  the  8259  should  be  programmed  by  sending  Initialization  Command  Word  (ICW)
and Operational Command Word (OCW). These command words will inform 8259 about the following,

* Type of interrupt signal (Level triggered / Edge triggered).

* Type of processor (8085/8086).

* Call address and its interval (4 or 8)

* Masking of interrupts.

* Priority of interrupts.

* Type of end of interrupts.

•    Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any one of the interrupt lines IR0-IR7  it checks for its priority and also checks whether it
is masked or not.

•    If  the  previous  interrupt  is  completed  and  if  the  current  request  has  highest  priority  and unmasked, then it is serviced.

•    For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085.

•    In response it expects an acknowledge INTA (low) from the processor.

•    When the processor accepts the interrupt, it sends three INTA (low) one by one.

•    In response to  first, second and third INTA (low) signals, the  8259 will supply CALL opcode, low byte of call address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and load the CALL address in PC and start executing the interrupt service routine stored in this call address.

FEATURES & FUNCTIONAL BLOCK DIAGRAM OF 8259 PROCESSOR

1. It is programmed to work with either 8085 or 8086 processor. 

2. It manage 8-interrupts according to the instructions written into its control registers.

3.  In  8086  processor,  it  supplies  the  type  number  of  the  interrupt  and  the  type  number  is programmable.  In  8085  processor,  the  interrupt  vector  address  is  programmable.  The priorities of the interrupts are programmable.

4. The interrupts can be masked or unmasked individually.

5. The 8259s can be cascaded to accept a maximum of 64 interrupts.

FUNCTIONAL BLOCK DIAGRAM OF 8259:

•    It has eight functional blocks. They are,

1.   Control logic

2.   Read Write logic

3.   Data bus buffer

4.   Interrupt Request Register (IRR)

5.   In-Service Register (ISR)

6.   Interrupt Mask Register (IMR)

7.   Priority Resolver (PR)

8.   Cascade buffer.

The data bus and its buffer are used for the following activities.

1.   The processor sends control word to data bus buffer through D0-D7.

2.   The processor read status word from data bus buffer through D0-D7.

3.  From the  data  bus  buffer  the  8259  send  type  number  (in  case  of  8086)  or  the  call opcode and    address (in case of 8085) through D0-D7 to the processor.

•    The processor uses the RD (low), WR (low) and A0 to read or write 8259.

•    The 8259 is selected by CS (low).

•    The  IRR  has  eight  input  lines  (IR0-IR7)  for  interrupts.  When  these  lines  go  high,  the request is stored in IRR. It registers a request only if the interrupt is unmasked.

•    Normally  IR0  has  highest  priority  and  IR7  has  the  lowest  priority.  The  priorities  of  the interrupt request input are also programmable.

•    First  the  8259  should  be  programmed  by  sending  Initialization  Command  Word  (ICW)
and Operational Command Word (OCW). These command words will inform 8259 about the following,

* Type of interrupt signal (Level triggered / Edge triggered).
* Type of processor (8085/8086).
* Call address and its interval (4 or 8)
* Masking of interrupts.
* Priority of interrupts.
* Type of end of interrupts.


•    The  interrupt  mask  register  (IMR)  stores  the  masking  bits  of  the  interrupt  lines  to  be masked. The relevant information is send by the processor through OCW.

•    The in-service register keeps track of which interrupt is currently being serviced.

•    The  priority  resolver  examines  the  interrupt  request,  mask  and  in-service  registers  and determines whether INT signal should be sent to the processor or not.

•    The cascade buffer/comparator is used to expand the interrupts of 8259.

•    In cascade connection one 8259 will be directly interrupting 8086 and it is called master
8259.

•    To  each  interrupt  request  input  of  master  8259  (IR0-IR7),  one  slave  8259  can  be connected. The 8259s interrupting the master 8259 are called slave 8259s.

•    Each 8259 has its own addresses so that each 8259 can be programmed independently by sending command words and independently the status bytes can be read from it.

•    The  cascade  pins  (CAS0,  CAS1   and  CAS2)  from  the  master  are  connected  to  the corresponding pins of the slave.

•    For the slave 8259, the SP (low) / EN (low) pin is tied low to let the device know that it is
a slave.

•    The SP (low) / EN (low) pin can be used as input or output signal.

•    In non-buffered mode it is used as input signal and tied to logic-I in master 8259 and logic-0 in slave 8259.

•    In buffered mode it  is used as output signal to disable the data buffers while data is transferred from 8259A to the CPU.

Cascade Connection of 8059

Interfacing of 8257 with 8085 processor

•    A simple schematic for interfacing the 8257 with 8085 processor is shown.

•    The 8257 can be either memory mapped or I/O mapped in the system.

•    In the schematic shown in figure is I/O mapped in the system.

•    Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

•    The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.

•    The address line A7 and the control signal IO/M (low) are used as enable for decoder.

•    The  D0-D7  lines  of  8257  are  connected  to  data  bus  lines  D0-D7  for  data  transfer  with processor during programming mode.

•    These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15  during
the DMA mode.

•    The 8257 also supply two control signals ADSTB and AEN to latch the address supplied
by it during DMA mode on external latches.

•    Two  8-bit  latches  are  provided  to  hold  the  16-bit  memory  address  during  DMA  mode. During DMA mode, the AEN signal is also used to disable the buffers and latches used
for address, data and control signals of the processor.

•    The  8257  provide  separate  read  and  write  control  signals  for  memory  and  I/O  devices during DMA.

•    Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by
a suitable logic circuit to generate separate read and write control signals f memory and
I/O devices.

•    The output clock of 8085 processor should be inverted and supplied to 8257 clock input for proper operation.

•    The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD
request to the processor.

•    The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the acknowledge signal from the processor once the HOLD request is accepted.

•    The RESET OUT of 8085 processor is connected to RESET of 8257.

•    The I/O addresses of the internal registers of 8257 are listed in table.

PROGRAMMABLE DMA CONTROLLER - INTEL 8257:

•    It is a device to transfer the data directly between IO device and memory without through
the CPU. So it performs a high-speed data transfer between memory and I/O device.
•    The features of 8257 is,

1.   The 8257 has four channels and so it can be used to provide DMA to four I/O
devices
2.   Each channel can be independently programmable to transfer up to 64kb of data
by DMA.
3.   Each  channel  can  be  independently  perform  read  transfer,  write  transfer  and verify transfer.

•    It is a 40 pin IC and the pin diagram is,

Functional Block Diagram of 8257:

•    The functional block diagram of 8257 is shown in fig.
•    The  functional  blocks  of  8257  are  data  bus  buffer,  read/write  logic,  control  logic, priority resolver and four numbers of DMA channels.
•    Each  channel  has  two  programmable  16-bit  registers  named  as  address  register  and count register.

•    Address register is used to store the starting address of memory location for DMA data transfer.
•    The    address    in    the    address    register    is    automatically    incremented    after    every read/write/verify transfer.
•    The count register is used to count the number of byte or word transferred by DMA
•    The format of count register is,

•    14-bits B0-B13  is used to  count value and  a 2-bits is used for indicate the type of DMA
transfer (Read/Write/Veri1 transfer).
•    In read transfer the data is transferred from memory to I/O device.
•    In write transfer the data is transferred from I/O device to memory.
•    Verification   operations   generate   the   DMA   addresses   without   generating   the   DMA
memory and I/O control signals.
•    The 8257 has two eight bit registers called mode set register and status register.
•    The format of mode set register is,

•    The use of mode set register is,

1.   Enable/disable a channel.
2.   Fixed/rotating priority
3.   Stop DMA on terminal count.
4.   Extended/normal write time.
5.   Auto reloading of channel-2.

•    The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1, 2
and 3 respectively. A one in these bit position will enable a particular channel and a zero
will disable it
•    If the bit B4 is set to one, then the channels will have rotating priority and if it zero then the channels wilt have fixed priority.

1.  In rotating priority after servicing a channel its priority is made as lowest.
2.  In fixed priority the channel-0 has highest priority and channel-2 has lowest priority.

•    If the bit B5  is set to one, then the timing of low write signals (MEMW and IOW) will be extended.
•    If the bit B6 is set to one then the DMA operation is stopped at the terminal count.
•    The bit B7 is used to select the auto load feature for DMA channel-2.
•    When bit B7  is set to one, then the content of channel-3 count and address registers are loaded  in  channel-2  count  and  address  registers  respectively  whenever  the  channel-2
reaches terminal count. When this mode is activated the number of channels available for
DMA reduces from four to three.
•    The format of status register of 8257 is shown in fig.

•    The  bit  B0,  B1,  B2,  and  B3  of  status  register  indicates  the  terminal  count  status  of channel-0, 1,2 and 3 respectively. A one in these bit positions indicates that the particular
channel has reached terminal count.
•    These status bits are cleared after a read operation by microprocessor.
•    The bit B4  of status register is called update flag and a one in this bit position indicates that  the  channel-2  register  has  been  reloaded  from  channel-3  registers  in  the  auto  load mode of operation.
•    The internal addresses of the registers of 8257 are listed in table.

Interfacing 8251A to 8086 Processor

•    The chip select for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A5, A6  and A7 are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 825lA.

•    The address line A0 and the control signal M/IO(low) are used as enable for decoder.

•    The line A1 of 8086 is connected to C/D(low) of 8251A to provide the internal addresses.

•    The lines D0 – D7 connected to D0 – D7 of the processor to achieve parallel data transfer.

•    The RESET and clock signals are supplied by 8284 clock generator. Here the processor clock  is  directly  connected  to  8251A.  This  clock  controls  the  parallel  data  transfer
between the processor and 825lA.

•    8251A in I/O mapped in the system is shown in the figure.

•    The peripheral clock (PCLK) supplied by 8284, is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

•    In 8251A the transmission and reception baud rates can be different or same.

•    The TTL logic levels of the serial data lines  and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then
terminated on a standard 9-pin D-.type connector.

•    The device, which requires serial communication with processor, can be connected to this
9-pin D-type connector using 9-core cable.

•    The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

 •    The I/O addresses allotted to the internal devices of 8251A are listed in table.

Interfacing Intel 8251A with 8085 Processor

The 825 1A can be either memory mapped or I/O mapped in the system.

•    8251A in I/O mapped in the system is shown in the figure.

•    Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

•    The address lines A4, A5  and A6  are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 8251A.

•    The address line A7  and the control signal IO / M(low) are used as enable for decoder.

•    The address line  A0  of 8085 is connected to  C/D(low) of 8251A to provide the internal addresses.

•    The data lines D0  – D7  are connected to D0  – D7  of the processor to achieve parallel data transfer.

•    The RESET and clock signals are supplied by the processor. Here the processor clock is directly  connected  to  8251A.  This  clock  controls  the  parallel  data  transfer  between  the processor and 8251A.

•    The output clock signal of 8085 is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

•    The TTL logic levels of the serial data lines  and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then terminated on a standard 9-pin D-.type connector.

•    In 8251A the transmission and reception baud rates can be different or same.

•    The device which requires serial communication with processor can be connected to this
9-pin D-type connector using 9-core cable.

•    The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

•    I/O addresses of 8251A interfaced to 8085 is,

USART-INTEL 8251A MICROPROCESSOR

The  8251A  is  a  programmable  serial  communication  interface  chip  designed  for synchronous and asynchronous serial data communication.It supports the serial transmission of data.It is packed in a 28 pin DIP.

Pin Diagram of 8251A

Block Diagram:

The functional block diagram of 825 1A consists five sections. They are

•    Read/Write control logic
•    Transmitter
•    Receiver
•    Data bus buffer
•    Modem control.

  The functional block diagram is,

Functional block diagram of 8251A-USART

Read/Write control logic:

•    The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.

•    It monitors the data flow.

•    This  section  has  three  registers  and  they  are  control  register,  status  register  and  data buffer.

•    The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.

•    When C/D(low) is high, the control register is selected for writing control word or reading status word.

•    When C/D(low) is low, the data buffer is selected for read/write operation.

•    When the reset is high, it forces 8251A into the idle mode.

•    The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section:

•    The transmitter section accepts parallel data from CPU and converts them into serial data.

•    The  transmitter  section  is  double  buffered,  i.e.,  it  has  a  buffer  register  to  hold  an  8-bit parallel  data  and  another  register  called  output  register  to  convert  the  parallel  data  into
serial bits.

•    When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

•    If buffer register is empty, then TxRDY is goes to high.

•    If output register is empty then TxEMPTY goes to high.

•    The  clock  signal,  TxC  (low)  controls  the  rate  at  which  the  bits  are  transmitted  by  the
USART.

•    The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

•    The receiver section accepts serial data and convert them into parallel data.

•    The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

•    When the RxD line goes low, the control logic assumes it as a START bit, waits for half a
bit time and samples the line again.

•    If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

•    The CPU reads the parallel data from the buffer register.

•    When the input register loads a parallel data to buffer register, the RxRDY line goes high.

•    The clock signal RxC (low) controls the rate at which bits are received by the USART.

•    During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

•    During synchronous mode, the signal  SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

•    The MODEM control unit allows to interface  a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

•    This unit takes care of handshake signals for MODEM interface.

KEYBOARD AND DISPLAY INTERFACE USING INTEL 8279 MICROPROCESSOR

In a microprocessor b   system,   when   keyboard   and   7-segment   LED   display   is interfaced using ports or latches then the processor has to carry the following task.

• Keyboard scanning
• Key debouncing
• Key code generation
• Sending display code to LED
• Display refreshing

Interfacing 8279 with 8085 processor:

 •    A  typical  Hexa  keyboard  and  7-segment  LED  display  interfacing  circuit  using  8279  is shown.

•    The  circuit  can  be  used  in  8085  microprocessor  system  and  consist  of  16  numbers  of hexa-keys and 6 numbers of 7-segment LEDs.

•    The 7-segment LEDs can be used to display six digit alphanumeric character.

•    The 8279 can be either memory mapped or I/O mapped in the system. In the circuit shown
is the 8279 is I/O mapped.

•    The address line A0 of the system is used as A0 of 8279.

•    The clock signal for  8279 is obtained by dividing the output clock signal of  8085 by  a clock divider circuit.

•    The chip select signal is obtained from the I/O address decoder of the 8085 system. The chip select signals for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A4, A5 and A6 are used as input to decoder.

•    The address line A7 and the control signal IO/M (low) are used as enable for decoder.

•    The chip select signal IOCS-3 is used to select 8279.

•    The I/O address of the internal devices of 8279 are shown in table.

•    The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in encoded  scan.  (Because  in  decoded  scan,  only  4  numbers  of  7-segment  LEDs  can  be interfaced):

•    In encoded scan the output of scan lines will be binary count. Therefore an external, 3-to-
8 decoder is used to decode the scan lines SL0, SL1  and SL2  of 8279 to produce eight scan lines S0 to S7.

•    The decoded scan lines S0 and S1  are common for keyboard and display.

•    The decoded scan lines S2  to S5  are used only for display and the decoded scan lines S6
and S7 are not used in the system.

•    Anode and Cathode drivers are provided to take care of the current requirement of LEDs.

•    The pnp transistors, BC 158 are used as driver transistors.

•    The anode drivers are called segment drivers and cathode drivers are called digit drivers.

•    The 8279 output the display code for one digit through its output lines (OUT A0  to OUT
A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

•    The display code is inverted by segment drivers and sent to segment bus.

•    The  scan  code  is  decoded  by  the  decoder  and  turns  ON  the  corresponding digit  driver. Now  one  digit  of  the  display  character  is  displayed.  After  a  small  interval  (10  milli- second, typical), the display is turned OFF (i.e., display is blanked) and the above process
is repeated for next digit. Thus multiplexed display is performed by 8279.

•    The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as columns and decoded scan lines S0 and S1 as rows.

•    A hexa key is placed at the crossing point of each row and column. A key press will short the row and column. Normally the column and row line will be high.

•    During scanning the 8279 will output binary  count on SL0  to SL3, which is decoded  by decoder to make a row as zero. When a row is zero the 8279 reads the columns. If there is
a key press then the corresponding column will be zero.

•    If 8279 detects a key press then it wait for debounce time and again read the columns to generate key code.

•    In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key press. The keycode consist of the binary value of the column and row in which the key is found and the status of shift and control key.

•    After a scan time, the next row is made zero and the above process is repeated and so on. Thus 8279 continuously scan the keyboard.

Interfacing 8279 with 8086 processor:

• A  typical  Hexa  keyboard  and  7-segment  LED  display  interfacing  circuit  using  8279  f
8086 based system is shown.

•        The system consists of 16 numbers of hexa-keys and numbers of 7-segment LEDs. The 7- segment LEDs can be used to display eight-digit alphanumeric character.

•    The 8279 can be either memory mapped or I/O mapped in the system. In the circuit shown
is I/O mapped.

•    The address line A1 of the system is used as A0 of 8279.

•    The clock signal for 8279 is obtained by dividing the PCLK (peripheral clock) of 8284 by
a clock divider circuit.

•    The chip select signals, for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A5, A6 and A7 are used as input to decoder.

•    The address line A0  and the control signal M  /IO (low) are used as enable for decoder. The chip select signal IOCS-3 is used to select 8279.

•    The I/O address of the internal devices of 8279 is shown in table.

•    The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in encoded  scan.  (Because  in  decoded  scan,  only  4  numbers  of  7-segment  LEDs  can  be interfaced):

•    In encoded scan the output of scan lines will be binary count. Therefore an external, 3-to-
8 decoder is used to decode the scan lines SL0, SL1  and SL2  of 8279 to produce eight scan lines S0 to S7.

•    The decoded scan lines S0 and S1  are common for keyboard and display.

•    The decoded scan lines S2  to S5  are used only for display and the decoded scan lines S6
and S7 are not used in the system.

•    Anode and Cathode drivers are provided to take care of the current requirement of LEDs.

•    The pnp transistors, BC 158 are used as driver transistors.

•    The anode drivers are called segment drivers and cathode drivers are called digit drivers.

•    The 8279 output the display code for one digit through its output lines (OUT A0  to OUT
A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

•    The display code is inverted by segment drivers and sent to segment bus.

•    The  scan  code  is  decoded  by  the  decoder  and  turns  ON  the  corresponding digit  driver. Now  one  digit  of  the  display  character  is  displayed.  After  a  small  interval  (10  milli-
second, typical), the display is turned OFF (i.e., display is blanked) and the above process
is repeated for next digit. Thus multiplexed display is performed by 8279.

•    The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as columns and decoded scan lines S0 and S1 as rows.

•    A hexa key is placed at the crossing point of each row and column. A key press will short the row and column. Normally the column and row line will be high.

•    During scanning the 8279 will output binary  count on SL0  to SL3, which is decoded  by decoder to make a row as zero. When a row is zero the 8279 reads the columns. If there is
a key press then the corresponding column will be zero.

•    If 8279 detects a key press then it wait for debounce time and again read the columns to generate key code.

•    In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key press. The keycode consist of the binary value of the column and row in which the key is found
and the status of shift and control key.

•    After a scan time, the next row is made zero and the above process is repeated and so on. Thus 8279 continuously scan the keyboard.