APPLICATIONS OF 8085 MICROPROCESSOR (DAC INTERFACE)

DAC  INTERFACE 

In many applications, the microprocessor has to produce analog signals for controlling certain analog devices. Basically the microprocessor system can produce only digital signals. In order to convert the digital signal to analog signal a Digital-to-Analog Converter. (DAC) has to be employed.

The DAC will accept a digital (binary) input and convert to analog voltage or current. Every DAC will have "n" input lines and an analog output.

The DAC require a reference analog voltage (Vref) or current (Iref) source.

The smallest possible analog value that can be represented by the n-bit binary code is called resolution. The resolution of DAC with n-bit binary input is 1/2n of reference analog value. Every analog output will be a multiple of the resolution. In some converters the input reference analog signal will be multiplied or divided by a constant to get full scale value. Now the resolution will be 1/2n of full scale value.

For example,
Consider an 8-bit DAC with reference analog voltage of 5 volts.
Now the resolution of the DAC is (1/28) x 5 volts.
The 8-bit digital input can take, 28 = 256 different values.
The analog values for all possible digital input are as shown in table below.

The maximum input digital signal will have an analog value which is equal to reference analog value minus resolution.

The digital-to-analog converters can be broadly classified into three categories, and they are

•    Current output
•    Voltage output 
•    Multiplying type

The current output DAC provides an analog current as output signal.
In voltage output DAC, the analog current signal is internally converted to voltage signal.

In multiplying type DAC, the output is given by the product of the input signal and the reference source and the product is linear over a broad range. Basically, there is not much difference between these three types and any DAC can be viewed as multiplying DAC.

Typical DAC circuit:

The basic components of a DAC are resistive network with appropriate values, switches, a reference source and a current to voltage converter as shown in figure below.

The switches in the circuit of figure above can be transistors which connects the resistance either to ground or Vref.  The resistors are connected in such a way that for any number of inputs, the total current is in binary proportion. The operational amplifier converts the current to a voltage signal V0, which can be calculated from the following equation. 

The circuit of figure shown above can be modified as 8-bitDAC, by increasing the number of R/2R ladder. For an 8-bit DAC the output voltage is given by

The time required for converting the digital signal to analog signal is called conversion time. It depends on the response time of the switching transistors and the output amplifier. If the DAC is interfaced to microprocessor then the digital data (Signal) should remain at the input of DAC, until the conversion is complete. Hence to hold the data a latch is provided at the input of DAC. 

The Digital-to-Analog converters compatible to microprocessors are available with or without internal latch and I to V converting amplifier. The AD558 of Analog Devices is an example of 8-bit DAC with an internal latch and I to V converting amplifiers. The output of AD558 is an analog voltage signal.     The AD558 can be directly interfaced to 8085 microprocessor bus and it requires only two control signals: Chip Select (CS) and Chip Enable (CE). [No handshake signals are necessary for interfacing a DAC. The time between loading two digital data to DAC is controlled by software time delay].

The DAC0808 of National Semiconductor Corporation is an example of 8-bit DAC without internal latch and I to V converting amplifier. The internal block diagram and the pin configuration of DAC0808 are shown in figure below.

The DAC0800 can be interfaced to 8085 system through an 8-bit latch as shown in figure below. The chip select (CS) signal from the decoder of the microprocessor system is delayed and inverted to clock the latch. If the DAC is memory mapped then the CS is from memory decoder. If the DAC is I/O mapped then CS is from I/O decoder. 

 

The processor sends an address, which is decoded by decoder in the microprocessor system to produce chip select signal. Then the processor sends a digital data to latch. The buffer and inverter will produce sufficient delay for CS signal so that, the latch is clocked only after the data is arrived at the input lines of the latch. When the latch is clocked the digital data is send to DAC. The DAC will produce a corresponding current signal, which is converted to voltage signal by the op-amp 741. The typical settling time of DAC0800 is 150nsec. Therefore the processor need not wait for loading next data.

INTERFACING 8259 WITH 8085 MICROPROCESSOR:

•    It requires two internal address and they are A =0 or A = 1.

•    It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085 is shown in figure is I/O mapped in the system.

•    The low order data bus lines D0-D7 are connected to D0-D7 of 8259.

•    The  address  line  A0  of the  8085  processor  is  connected  to  A0   of  8259  to  provide  the  internal address.

•    The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for
8259.

•    The address lines A4, A5  and A6  are used as input to decoder.

•    The control signal IO/M (low) is used as logic high enables for decoder and the address line A7  is used as logic low enable for decoder.

•    The I/O ad4ressès of 8259 are shown in table-8.5.

Working of 8259 with 8085 processor:

•    First  the  8259  should  be  programmed  by  sending  Initialization  Command  Word  (ICW)
and Operational Command Word (OCW). These command words will inform 8259 about the following,

* Type of interrupt signal (Level triggered / Edge triggered).

* Type of processor (8085/8086).

* Call address and its interval (4 or 8)

* Masking of interrupts.

* Priority of interrupts.

* Type of end of interrupts.

•    Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any one of the interrupt lines IR0-IR7  it checks for its priority and also checks whether it
is masked or not.

•    If  the  previous  interrupt  is  completed  and  if  the  current  request  has  highest  priority  and unmasked, then it is serviced.

•    For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085.

•    In response it expects an acknowledge INTA (low) from the processor.

•    When the processor accepts the interrupt, it sends three INTA (low) one by one.

•    In response to  first, second and third INTA (low) signals, the  8259 will supply CALL opcode, low byte of call address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and load the CALL address in PC and start executing the interrupt service routine stored in this call address.

PROGRAMMABLE DMA CONTROLLER - INTEL 8257:

•    It is a device to transfer the data directly between IO device and memory without through
the CPU. So it performs a high-speed data transfer between memory and I/O device.
•    The features of 8257 is,

1.   The 8257 has four channels and so it can be used to provide DMA to four I/O
devices
2.   Each channel can be independently programmable to transfer up to 64kb of data
by DMA.
3.   Each  channel  can  be  independently  perform  read  transfer,  write  transfer  and verify transfer.

•    It is a 40 pin IC and the pin diagram is,

Functional Block Diagram of 8257:

•    The functional block diagram of 8257 is shown in fig.
•    The  functional  blocks  of  8257  are  data  bus  buffer,  read/write  logic,  control  logic, priority resolver and four numbers of DMA channels.
•    Each  channel  has  two  programmable  16-bit  registers  named  as  address  register  and count register.

•    Address register is used to store the starting address of memory location for DMA data transfer.
•    The    address    in    the    address    register    is    automatically    incremented    after    every read/write/verify transfer.
•    The count register is used to count the number of byte or word transferred by DMA
•    The format of count register is,

•    14-bits B0-B13  is used to  count value and  a 2-bits is used for indicate the type of DMA
transfer (Read/Write/Veri1 transfer).
•    In read transfer the data is transferred from memory to I/O device.
•    In write transfer the data is transferred from I/O device to memory.
•    Verification   operations   generate   the   DMA   addresses   without   generating   the   DMA
memory and I/O control signals.
•    The 8257 has two eight bit registers called mode set register and status register.
•    The format of mode set register is,

•    The use of mode set register is,

1.   Enable/disable a channel.
2.   Fixed/rotating priority
3.   Stop DMA on terminal count.
4.   Extended/normal write time.
5.   Auto reloading of channel-2.

•    The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1, 2
and 3 respectively. A one in these bit position will enable a particular channel and a zero
will disable it
•    If the bit B4 is set to one, then the channels will have rotating priority and if it zero then the channels wilt have fixed priority.

1.  In rotating priority after servicing a channel its priority is made as lowest.
2.  In fixed priority the channel-0 has highest priority and channel-2 has lowest priority.

•    If the bit B5  is set to one, then the timing of low write signals (MEMW and IOW) will be extended.
•    If the bit B6 is set to one then the DMA operation is stopped at the terminal count.
•    The bit B7 is used to select the auto load feature for DMA channel-2.
•    When bit B7  is set to one, then the content of channel-3 count and address registers are loaded  in  channel-2  count  and  address  registers  respectively  whenever  the  channel-2
reaches terminal count. When this mode is activated the number of channels available for
DMA reduces from four to three.
•    The format of status register of 8257 is shown in fig.

•    The  bit  B0,  B1,  B2,  and  B3  of  status  register  indicates  the  terminal  count  status  of channel-0, 1,2 and 3 respectively. A one in these bit positions indicates that the particular
channel has reached terminal count.
•    These status bits are cleared after a read operation by microprocessor.
•    The bit B4  of status register is called update flag and a one in this bit position indicates that  the  channel-2  register  has  been  reloaded  from  channel-3  registers  in  the  auto  load mode of operation.
•    The internal addresses of the registers of 8257 are listed in table.

Interfacing Intel 8251A with 8085 Processor

The 825 1A can be either memory mapped or I/O mapped in the system.

•    8251A in I/O mapped in the system is shown in the figure.

•    Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

•    The address lines A4, A5  and A6  are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 8251A.

•    The address line A7  and the control signal IO / M(low) are used as enable for decoder.

•    The address line  A0  of 8085 is connected to  C/D(low) of 8251A to provide the internal addresses.

•    The data lines D0  – D7  are connected to D0  – D7  of the processor to achieve parallel data transfer.

•    The RESET and clock signals are supplied by the processor. Here the processor clock is directly  connected  to  8251A.  This  clock  controls  the  parallel  data  transfer  between  the processor and 8251A.

•    The output clock signal of 8085 is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

•    The TTL logic levels of the serial data lines  and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then terminated on a standard 9-pin D-.type connector.

•    In 8251A the transmission and reception baud rates can be different or same.

•    The device which requires serial communication with processor can be connected to this
9-pin D-type connector using 9-core cable.

•    The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

•    I/O addresses of 8251A interfaced to 8085 is,

USART-INTEL 8251A MICROPROCESSOR

The  8251A  is  a  programmable  serial  communication  interface  chip  designed  for synchronous and asynchronous serial data communication.It supports the serial transmission of data.It is packed in a 28 pin DIP.

Pin Diagram of 8251A

Block Diagram:

The functional block diagram of 825 1A consists five sections. They are

•    Read/Write control logic
•    Transmitter
•    Receiver
•    Data bus buffer
•    Modem control.

  The functional block diagram is,

Functional block diagram of 8251A-USART

Read/Write control logic:

•    The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.

•    It monitors the data flow.

•    This  section  has  three  registers  and  they  are  control  register,  status  register  and  data buffer.

•    The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.

•    When C/D(low) is high, the control register is selected for writing control word or reading status word.

•    When C/D(low) is low, the data buffer is selected for read/write operation.

•    When the reset is high, it forces 8251A into the idle mode.

•    The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section:

•    The transmitter section accepts parallel data from CPU and converts them into serial data.

•    The  transmitter  section  is  double  buffered,  i.e.,  it  has  a  buffer  register  to  hold  an  8-bit parallel  data  and  another  register  called  output  register  to  convert  the  parallel  data  into
serial bits.

•    When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

•    If buffer register is empty, then TxRDY is goes to high.

•    If output register is empty then TxEMPTY goes to high.

•    The  clock  signal,  TxC  (low)  controls  the  rate  at  which  the  bits  are  transmitted  by  the
USART.

•    The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

•    The receiver section accepts serial data and convert them into parallel data.

•    The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

•    When the RxD line goes low, the control logic assumes it as a START bit, waits for half a
bit time and samples the line again.

•    If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

•    The CPU reads the parallel data from the buffer register.

•    When the input register loads a parallel data to buffer register, the RxRDY line goes high.

•    The clock signal RxC (low) controls the rate at which bits are received by the USART.

•    During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

•    During synchronous mode, the signal  SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

•    The MODEM control unit allows to interface  a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

•    This unit takes care of handshake signals for MODEM interface.

KEYBOARD AND DISPLAY INTERFACE USING INTEL 8279 MICROPROCESSOR

In a microprocessor b   system,   when   keyboard   and   7-segment   LED   display   is interfaced using ports or latches then the processor has to carry the following task.

• Keyboard scanning
• Key debouncing
• Key code generation
• Sending display code to LED
• Display refreshing

Interfacing 8279 with 8085 processor:

 •    A  typical  Hexa  keyboard  and  7-segment  LED  display  interfacing  circuit  using  8279  is shown.

•    The  circuit  can  be  used  in  8085  microprocessor  system  and  consist  of  16  numbers  of hexa-keys and 6 numbers of 7-segment LEDs.

•    The 7-segment LEDs can be used to display six digit alphanumeric character.

•    The 8279 can be either memory mapped or I/O mapped in the system. In the circuit shown
is the 8279 is I/O mapped.

•    The address line A0 of the system is used as A0 of 8279.

•    The clock signal for  8279 is obtained by dividing the output clock signal of  8085 by  a clock divider circuit.

•    The chip select signal is obtained from the I/O address decoder of the 8085 system. The chip select signals for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A4, A5 and A6 are used as input to decoder.

•    The address line A7 and the control signal IO/M (low) are used as enable for decoder.

•    The chip select signal IOCS-3 is used to select 8279.

•    The I/O address of the internal devices of 8279 are shown in table.

•    The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in encoded  scan.  (Because  in  decoded  scan,  only  4  numbers  of  7-segment  LEDs  can  be interfaced):

•    In encoded scan the output of scan lines will be binary count. Therefore an external, 3-to-
8 decoder is used to decode the scan lines SL0, SL1  and SL2  of 8279 to produce eight scan lines S0 to S7.

•    The decoded scan lines S0 and S1  are common for keyboard and display.

•    The decoded scan lines S2  to S5  are used only for display and the decoded scan lines S6
and S7 are not used in the system.

•    Anode and Cathode drivers are provided to take care of the current requirement of LEDs.

•    The pnp transistors, BC 158 are used as driver transistors.

•    The anode drivers are called segment drivers and cathode drivers are called digit drivers.

•    The 8279 output the display code for one digit through its output lines (OUT A0  to OUT
A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

•    The display code is inverted by segment drivers and sent to segment bus.

•    The  scan  code  is  decoded  by  the  decoder  and  turns  ON  the  corresponding digit  driver. Now  one  digit  of  the  display  character  is  displayed.  After  a  small  interval  (10  milli- second, typical), the display is turned OFF (i.e., display is blanked) and the above process
is repeated for next digit. Thus multiplexed display is performed by 8279.

•    The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as columns and decoded scan lines S0 and S1 as rows.

•    A hexa key is placed at the crossing point of each row and column. A key press will short the row and column. Normally the column and row line will be high.

•    During scanning the 8279 will output binary  count on SL0  to SL3, which is decoded  by decoder to make a row as zero. When a row is zero the 8279 reads the columns. If there is
a key press then the corresponding column will be zero.

•    If 8279 detects a key press then it wait for debounce time and again read the columns to generate key code.

•    In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key press. The keycode consist of the binary value of the column and row in which the key is found and the status of shift and control key.

•    After a scan time, the next row is made zero and the above process is repeated and so on. Thus 8279 continuously scan the keyboard.

Interfacing 8279 with 8086 processor:

• A  typical  Hexa  keyboard  and  7-segment  LED  display  interfacing  circuit  using  8279  f
8086 based system is shown.

•        The system consists of 16 numbers of hexa-keys and numbers of 7-segment LEDs. The 7- segment LEDs can be used to display eight-digit alphanumeric character.

•    The 8279 can be either memory mapped or I/O mapped in the system. In the circuit shown
is I/O mapped.

•    The address line A1 of the system is used as A0 of 8279.

•    The clock signal for 8279 is obtained by dividing the PCLK (peripheral clock) of 8284 by
a clock divider circuit.

•    The chip select signals, for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A5, A6 and A7 are used as input to decoder.

•    The address line A0  and the control signal M  /IO (low) are used as enable for decoder. The chip select signal IOCS-3 is used to select 8279.

•    The I/O address of the internal devices of 8279 is shown in table.

•    The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in encoded  scan.  (Because  in  decoded  scan,  only  4  numbers  of  7-segment  LEDs  can  be interfaced):

•    In encoded scan the output of scan lines will be binary count. Therefore an external, 3-to-
8 decoder is used to decode the scan lines SL0, SL1  and SL2  of 8279 to produce eight scan lines S0 to S7.

•    The decoded scan lines S0 and S1  are common for keyboard and display.

•    The decoded scan lines S2  to S5  are used only for display and the decoded scan lines S6
and S7 are not used in the system.

•    Anode and Cathode drivers are provided to take care of the current requirement of LEDs.

•    The pnp transistors, BC 158 are used as driver transistors.

•    The anode drivers are called segment drivers and cathode drivers are called digit drivers.

•    The 8279 output the display code for one digit through its output lines (OUT A0  to OUT
A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

•    The display code is inverted by segment drivers and sent to segment bus.

•    The  scan  code  is  decoded  by  the  decoder  and  turns  ON  the  corresponding digit  driver. Now  one  digit  of  the  display  character  is  displayed.  After  a  small  interval  (10  milli-
second, typical), the display is turned OFF (i.e., display is blanked) and the above process
is repeated for next digit. Thus multiplexed display is performed by 8279.

•    The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as columns and decoded scan lines S0 and S1 as rows.

•    A hexa key is placed at the crossing point of each row and column. A key press will short the row and column. Normally the column and row line will be high.

•    During scanning the 8279 will output binary  count on SL0  to SL3, which is decoded  by decoder to make a row as zero. When a row is zero the 8279 reads the columns. If there is
a key press then the corresponding column will be zero.

•    If 8279 detects a key press then it wait for debounce time and again read the columns to generate key code.

•    In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key press. The keycode consist of the binary value of the column and row in which the key is found
and the status of shift and control key.

•    After a scan time, the next row is made zero and the above process is repeated and so on. Thus 8279 continuously scan the keyboard.

INTEL 8279 MICROPROCESSOR - KEYBOARD/DISPLAY CONTROLLER

The INTEL 8279 is specially developed for interfacing keyboard and display devices
to 8085/8086/8088 microprocessor based system. The important features of 8279 are,

• Simultaneous keyboard and display operations.
• Scanned keyboard mode.
• Scanned sensor mode.
• 8-character keyboard FIFO.
• 1 6-character display.
• Right or left entry 1 6-byte display RAM.
• Programmable scan timing.

Block diagram of 8279:

•    The functional block diagram of 8279 is shown.

•    The four major sections of 8279 are keyboard, scan, display and CPU interface.

Keyboard section:

•    The keyboard section consists of eight return lines RL0 – RL7 that can be used to form the columns of a keyboard matrix.

•    It   has   two   additional   input   :   shift   and   control/strobe.   The   keys   are   automatically debounced.

•    The two operating modes of keyboard section are 2-key lockout and N-key rollover.

•    In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized.

•    In the N-key rollover mode simultaneous keys are recognized and their codes are stored in
FIFO.

•    The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.

•    The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,

•    In sensor  matrix mode the condition (i.e., open/close status) of 64  switches is stored in FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor.

Display section:

•    The display section has eight output lines divided into two groups A0-A3 and B0-B3.

•    The output lines can be used either as a single group of eight lines or as two  groups of four lines, in conjunction with the scan lines for a multiplexed display.

•    The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs.

•    The cathodes are connected to scan lines through driver transistors.

•    The display can be blanked by BD (low) line.

•    The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM.

Scan section:

•    The scan section has a scan counter and four scan lines, SL0 to SL3.

•    In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.

•    In encoded scan mode, the output of scan lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output.

•    The scan lines are common for keyboard and display.

•    The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a multiplexed display, to turn ON/OFF.

CPU interface section:

•    The CPU interface section takes care of data transfer between 8279 and the processor.

•    This section has eight bidirectional data lines DB0  to DB7  for data transfer between 8279
and CPU.

•    It  requires  two  internal  address  A  =0  for  selecting  data  buffer  and  A  =  1  for  selecting control register of8279.

•    The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.

•    It has an interrupt request line IRQ, for interrupt driven data transfer with processor.

•    The  8279  require  an  internal  clock  frequency  of  100  kHz.  This  can  be  obtained  by dividing the input clock by an internal prescaler.

•    The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.

Programming the 8279:

•    The  8279  can  be  programmed  to  perform  various  functions  through  eight  command words.

INTEL 8255 Programmable Peripheral Interface (PART-2)

Internal block diagram of 8255

The ports are grouped as Group A and Group B. The group A has port A, port C upper and its control circuit. The group B has port B, port C lower and its control circuit. The Read/Write control logic requires six control signals. These signals are given below.

RD (Read) :   This control signal enables the read operation.
                     When this signal is LOW, the microprocessor reads data from a selected I/O port of the 
                      8255A.

WR (Write):  This control signal enables the write operation.
                       When this signal goes LOW, the microprocessor writes into a selected I/O port
                       or the control register.

RESET:         This is an active HIGH signal.
                       It clears the control register and set all ports in the input mode.

CS, A0  and A1 : These are device select signals.
                             The CS is connected to the decoder in the system.
                             A0 and A1 are generally connected to A0 and A1 of the processor.

(Alternatively, A0 and A1 can be connected to any two-address lines of the processor).
8255 can be either Memory mapped or I/O mapped in the system.

A0 and A1 address lines can be made to select any one of the following four internal devices as shown on right side.

Programming 8255:
The 8255 has two control words, one for specifying 1/O functions and another for bit set/reset mode of port C. Both the control words are written in the same control register.

The control register differentiate them by the value of bit D7 .The bit set/reset control word does not affect the functions of ports A and B.

Bit D7 of the control register specifies either the 1/0 function or the bit set / reset function.
If bit D7 = 1, then the bits D6 – D0 determine 1/0 functions in various modes.
If bit D7 = 0, then the bits D6 – D0 determine the pin of port C to be set or reset.


The 8255 ports are programmed (or initialized) by writing a control word in the control register.

For setting 1/0 functions and mode of operation the 1/0 mode control word is send to control register. The format of the 1/0 mode set control word is shown below.

For setting/resetting (BSR mode) a pin of port C, the bit set/ reset control word is sent to control register. The format of bit set/reset control word is shown below.

 

The data transfer between the processor and the port can be either interrupt driven or through status check.

In the interrupt driven data transfer scheme, when the port is ready, it interrupts the processor for a read or write operation.

In status check technique, the processor polls the status of the port and checks whether the port is ready for data transfer or not. The status of the ports A and B can be known by reading the port C. When the port is ready for data transfer, the processors executes a read or write cycle.

INTEL 8255 Programmable Peripheral Interface (PART-1)

Intel 8255 is a programmable peripheral interface chip designed for parallel communication between microprocessor and I/O devices, which have a speed mismatch between each other.


Features of 8255:

•It has three 8-bit ports
•It can be operated in three different modes in I/O mode and in BSR mode

IC 8255 has three ports A, Band C. The ports A and B are 8 bit parallel ports. Port A can be programmed to work in any one of the three modes as input or output port. The three operating modes are

Mode-0  - Simple I/O port
Mode-l   - Handshake I/O port
Mode-2  - Bidirectional I/O port.

The port B can be programmed to work either in mode-0 or mode-1. The port C pins (8-pins) have different assignments depending on the mode of port A and B. If port A and B are programmed in mode-0, then the port C can perform anyone of the following function.

1. As 8 bit parallel port in mode-0 for input or output.
2. As two numbers of 4 bit parallel port in mode-O for input or output.
3. The individual pins of port C can be set or reset for various control applications.

The various functions (assignments) of port C during the different operating modes of port A and B are listed in Table below.

If ports A and Bare programmed in mode-l or mode-2, then some of the pins of port C are used for handshake signals and the remaining pins can be used as input/output lines or individually set/reset for control applications.



I/0 Modes of 8255

Mode-0: In this mode, all the three ports can be programmed either as input or output port. In mode-O, the outputs are latched and the inputs are not latched. The ports do not have handshake or Interrupt capability. The ports in mode-o can be used to interface DIP switches, Hexa-keypad, LED's and 7-segment LED's to the processor.

Mode-l: In this mode, only ports A & B can be programmed either as input or output port. In mode-1, handshake signals are exchanged between the processor and peripherals prior to data transfer. The port C pins are used for  handshake signals. Input and output data are latched. Interrupt driven data transfer scheme is possible.

8255 Handshake Input port (Mode 1)

8255 Handshake Output port (Mode 1)\

Mode-2: In this mode, the port will be a bi-directional port (i.e., the processor can perform both read and write operations with an I/O device connected to a port in mode-2).
Only port-A can be programmed to work in mode-2. Five pins of port C are used for handshake signals. This mode is used primarily in applications such as data transfer between two computers or floppy disk controller interface.

Pins & Signals of 8255

The pin description of 8255 is shown in figure below. It has 40 pins and requires a single +5V supply.

INTEL 8085 Processor - Question & Answers (part-1)

Consider a system in which the full memory space 64kb is utilized for EPROM memory. Interface the EPROM with 8085 processor.

• The memory capacity is 64 Kbytes. i.e
          2 n = 64 x 1000 bytes where n = address lines. So, n = 16.

• In this  system the entire 16  address  lines of the processor are connected to  address input pins of memory IC in order to address the internal locations of memory.

• The  chip  select  (CS)  pin  of  EPROM  is  permanently  tied  to  logic  low  (i.e.,  tied  to ground).

• Since the processor  is connected to EPROM, the active  low  RD pin  is connected to active low output enable pin of EPROM.

• The range of address for EPROM is 0000H to FFFFH.

Interfacing 64Kb EPROM with 8085

Consider a system in which the available 64kb memory space is equally divided between
EPROM and RAM. Interface the EPROM and RAM with 8085 processor.

•    Implement 32kb memory capacity of EPROM using single IC 27256.

•    32kb RAM capacity is implemented using single IC 62256.

•    The 32kb memory requires 15 address lines and so the address lines A0  – A14  of the processor are connected to 15 address pins of both EPROM and RAM.

•    The unused address line A15  is used as to chip select. If A15  is 1, it select RAM and If
A15  is 0, it select EPROM.

•    Inverter is used for selecting the memory.

•    The memory used is both Ram and EPROM, so the low RD and WR pins of processor are connected to low WE and OE pins of memory respectively.

•    The  address  range  of  EPROM  will  be  0000H  to  7FFFH  and  that  of  RAM  will  be
7FFFH to FFFFH.

Interfacing 32Kb EPROM and 32Kb RAM with 8085

Consider a system in which 32kb memory space is implemented using four numbers of
8kb memory. Interface the EPROM and RAM with 8085 processor.

•    The total memory capacity is 32Kb. So, let two number of 8kb n memory be EPROM and the remaining two numbers be RAM.

•    Each 8kb memory requires 13 address lines and so the address lines A0- A12  of the processor are connected to 13 address pins of all the memory.

•    The address lines and A13  – A14  can be decoded using a 2-to-4 decoder to generate four chip select signals.

•    These  four chip  select  signals can  be used to  select  one of the  four  memory IC at  any one time.

•    The address line A15  is used as enable for decoder.

•    The simplified schematic memory organization is shown

Interfacing 16Kb EPROM and 16Kb RAM with 8085

•    The address allotted to each memory IC is shown in following table.

There are two types for interfacing I/O devices:

1.   Memory mapped I/O device.
2.   Standard I/O mapped I/O device or isolated I/O mapping.

DECODER IN 8085 PROCESSOR

It is used to select the memory chip of processor during the execution of a program.

No of IC used for decoder is,

•   2-4 decoder (74LS139)
•   3-8 decoder (74LS138)

TYPICAL EPROM AND STATIC RAM

A typical semiconductor memory IC will have n address pins, m data pins (or output pins).

•Having two power supply pins (one for connecting required supply voltage (V and the other for connecting ground).

•The control signals needed for static RAM are chip select (chip enable), read control (output enable) and write control (write enable).

•The  control signals  needed  for  read  operation  in  EPROM are  chip  select  (chip  enable)  and read control (output enable).

STRING INSTRUCTIONS IN 8086 PROCESSORS

• REP / REPE / REPZ / REPNE / REPNZ
• MOVS / MOVSB / MOVSW
• CMPS / CMPSB / CMPSW
• SCAS / SCASB / SCASW
• LODS / LODSB / LODSW
• STOS / STOSB / STOSW

ADDRESSING MODES:

1. Addressing modes for accessing immediate and register data.
2. Addressing modes for accessing data in memory.
3. Addressing modes for accessing I/O ports.
4. Relative Addressing mode.
5. Implied Addressing mode.

(1). Addressing modes for accessing immediate and register data:

(i) Register addressing mode: The registers, which is having the data to be operated is specified in the instruction.

• The IP content is,  [IP]new = [IP]old + 000AH.
• The effective address is, [EA] = [IP]new + 000AH.
• The base address is, BA = [CS] x 1610
• The memory address is, MA = [EA] + [BA].
• Program control jump into the new MA.

(5) Implied Addressing:

• The instruction itself is having the data to be operated.
• Eg. : CLC – It clears the carry flag.

8086 Instruction Set Part (4-10)

 4. SHIFT INSTRUCTIONS

SAL / SHL:

•The mnemonics is SAL / SHL destination, count.

Bit Manipulation Instruction Set (Logical Instructions) In 8086 Processors

NOT:  The NOT instruction inverts each bit of a byte or a word. The destination can be register or a memory location.
        Eg. :                    ; AL = 0110 1100
        NOT AL            ; AL = 1001 0011

                                   ; CX = 10101111 0010 0010
        NOT CX            ; CX = 0101 0000 11011001

AND: This instruction logically ANDs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination.

                 Eg. :               ; AL = 1001 0011 = 93H
                                       ; BL = 0111 0101 = 75H
    AND BL, AL              ; AND Byte in AL with byte in BL
                                       ; BL = 0001 0001 = 11H

OR : This instruction logically ORs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination.

                Eg. :           ; AL =1001 0011 = 93H
                                  ; BL =0111 0101 = 75H
    OR BL, AL            ; OR byte in AL with byte in BL
                                  ; BL =1111 0111 = F7H

XOR : This instruction logically XORs each bit of the source byte or word with the corresponding bit in the destination and stores result in the destination.

TEST: This instruction logically ANDs each bit of the source byte or word with the corresponding bit in the destination and updates the flags but not stores results in anywhere.

                 Eg. :            ; AL = 1001 0011 = 93H
                                    ; BL = 0111 0101 = 75H
    AND BL, AL           ; AND Byte in AL with byte in BL
                                    ; Result = 0001 0001 = 11H (not stored)
                                    ; Z  = 0, P = 1 (flag affected))
    AND BX, AX          ;  AND word in AX with word in BX
                                    ; updates the flag and result is not stored.

Arithmetic Instruction Set In 8086 Processors

(a) Addition

Instructions:
ADD  – It add the destination and source contents.