A "MEDIA TO GET" ALL DATAS IN ELECTRICAL SCIENCE...!!: Features of 8086

Showing posts with label Features of 8086. Show all posts

Interfacing of 8257 with 8085 processor

•    A simple schematic for interfacing the 8257 with 8085 processor is shown.

•    The 8257 can be either memory mapped or I/O mapped in the system.

•    In the schematic shown in figure is I/O mapped in the system.

•    Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

•    The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.

•    The address line A7 and the control signal IO/M (low) are used as enable for decoder.

•    The D0-D7 lines of 8257 are connected to data bus lines D0-D7 for data transfer with processor during programming mode.

•    These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15 during
the DMA mode.

•    The 8257 also supply two control signals ADSTB and AEN to latch the address supplied
by it during DMA mode on external latches.

•    Two 8-bit latches are provided to hold the 16-bit memory address during DMA mode. During DMA mode, the AEN signal is also used to disable the buffers and latches used
for address, data and control signals of the processor.

•    The 8257 provide separate read and write control signals for memory and I/O devices during DMA.

•    Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by
a suitable logic circuit to generate separate read and write control signals f memory and
I/O devices.

•    The output clock of 8085 processor should be inverted and supplied to 8257 clock input for proper operation.

•    The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD
request to the processor.

•    The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the acknowledge signal from the processor once the HOLD request is accepted.

•    The RESET OUT of 8085 processor is connected to RESET of 8257.

•    The I/O addresses of the internal registers of 8257 are listed in table.

PROGRAMMABLE DMA CONTROLLER - INTEL 8257:

•    It is a device to transfer the data directly between IO device and memory without through
the CPU. So it performs a high-speed data transfer between memory and I/O device.
•    The features of 8257 is,

1.   The 8257 has four channels and so it can be used to provide DMA to four I/O
devices
2.   Each channel can be independently programmable to transfer up to 64kb of data
by DMA.
3.   Each channel can be independently perform read transfer, write transfer and verify transfer.

•    It is a 40 pin IC and the pin diagram is,

Functional Block Diagram of 8257:

•    The functional block diagram of 8257 is shown in fig.
•    The functional blocks of 8257 are data bus buffer, read/write logic, control logic, priority resolver and four numbers of DMA channels.
•    Each channel has two programmable 16-bit registers named as address register and count register.

•    Address register is used to store the starting address of memory location for DMA data transfer.
•    The    address    in    the    address    register    is    automatically    incremented    after    every read/write/verify transfer.
•    The count register is used to count the number of byte or word transferred by DMA
•    The format of count register is,

•    14-bits B0-B13 is used to count value and a 2-bits is used for indicate the type of DMA
transfer (Read/Write/Veri1 transfer).
•    In read transfer the data is transferred from memory to I/O device.
•    In write transfer the data is transferred from I/O device to memory.
•    Verification   operations   generate   the   DMA   addresses   without   generating   the   DMA
memory and I/O control signals.
•    The 8257 has two eight bit registers called mode set register and status register.
•    The format of mode set register is,

•    The use of mode set register is,

1.   Enable/disable a channel.
2.   Fixed/rotating priority
3.   Stop DMA on terminal count.
4.   Extended/normal write time.
5.   Auto reloading of channel-2.

•    The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1, 2
and 3 respectively. A one in these bit position will enable a particular channel and a zero
will disable it
•    If the bit B4 is set to one, then the channels will have rotating priority and if it zero then the channels wilt have fixed priority.

In rotating priority after servicing a channel its priority is made as lowest.
In fixed priority the channel-0 has highest priority and channel-2 has lowest priority.

•    If the bit B5 is set to one, then the timing of low write signals (MEMW and IOW) will be extended.
•    If the bit B6 is set to one then the DMA operation is stopped at the terminal count.
•    The bit B7 is used to select the auto load feature for DMA channel-2.
•    When bit B7 is set to one, then the content of channel-3 count and address registers are loaded in channel-2 count and address registers respectively whenever the channel-2
reaches terminal count. When this mode is activated the number of channels available for
DMA reduces from four to three.
•    The format of status register of 8257 is shown in fig.

•    The bit B0, B1, B2, and B3 of status register indicates the terminal count status of channel-0, 1,2 and 3 respectively. A one in these bit positions indicates that the particular
channel has reached terminal count.
•    These status bits are cleared after a read operation by microprocessor.
•    The bit B4 of status register is called update flag and a one in this bit position indicates that the channel-2 register has been reloaded from channel-3 registers in the auto load mode of operation.
•    The internal addresses of the registers of 8257 are listed in table.

Interfacing 8251A to 8086 Processor

•    The chip select for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A5, A6 and A7 are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 825lA.

•    The address line A0 and the control signal M/IO(low) are used as enable for decoder.

•    The line A1 of 8086 is connected to C/D(low) of 8251A to provide the internal addresses.

•    The lines D0 – D7 connected to D0 – D7 of the processor to achieve parallel data transfer.

•    The RESET and clock signals are supplied by 8284 clock generator. Here the processor clock is directly connected to 8251A. This clock controls the parallel data transfer
between the processor and 825lA.

•    8251A in I/O mapped in the system is shown in the figure.

•    The peripheral clock (PCLK) supplied by 8284, is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

•    In 8251A the transmission and reception baud rates can be different or same.

•    The TTL logic levels of the serial data lines and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then
terminated on a standard 9-pin D-.type connector.

•    The device, which requires serial communication with processor, can be connected to this
9-pin D-type connector using 9-core cable.

•    The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

•    The I/O addresses allotted to the internal devices of 8251A are listed in table.

Interfacing Intel 8251A with 8085 Processor

The 825 1A can be either memory mapped or I/O mapped in the system.

•    8251A in I/O mapped in the system is shown in the figure.

•    Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

•    The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 8251A.

•    The address line A7 and the control signal IO / M(low) are used as enable for decoder.

•    The address line A0 of 8085 is connected to C/D(low) of 8251A to provide the internal addresses.

•    The data lines D0 – D7 are connected to D0 – D7 of the processor to achieve parallel data transfer.

•    The RESET and clock signals are supplied by the processor. Here the processor clock is directly connected to 8251A. This clock controls the parallel data transfer between the processor and 8251A.

•    The output clock signal of 8085 is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

•    The TTL logic levels of the serial data lines and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then terminated on a standard 9-pin D-.type connector.

•    In 8251A the transmission and reception baud rates can be different or same.

•    The device which requires serial communication with processor can be connected to this
9-pin D-type connector using 9-core cable.

•    The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

•    I/O addresses of 8251A interfaced to 8085 is,

USART-INTEL 8251A MICROPROCESSOR

The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication.It supports the serial transmission of data.It is packed in a 28 pin DIP.

Pin Diagram of 8251A

Block Diagram:

The functional block diagram of 825 1A consists five sections. They are

•    Read/Write control logic
•    Transmitter
•    Receiver
•    Data bus buffer
•    Modem control.

The functional block diagram is,

Functional block diagram of 8251A-USART

Read/Write control logic:

•    The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.

•    It monitors the data flow.

•    This section has three registers and they are control register, status register and data buffer.

•    The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.

•    When C/D(low) is high, the control register is selected for writing control word or reading status word.

•    When C/D(low) is low, the data buffer is selected for read/write operation.

•    When the reset is high, it forces 8251A into the idle mode.

•    The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section:

•    The transmitter section accepts parallel data from CPU and converts them into serial data.

•    The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into
serial bits.

•    When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

•    If buffer register is empty, then TxRDY is goes to high.

•    If output register is empty then TxEMPTY goes to high.

•    The clock signal, TxC (low) controls the rate at which the bits are transmitted by the
USART.

•    The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

•    The receiver section accepts serial data and convert them into parallel data.

•    The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

•    When the RxD line goes low, the control logic assumes it as a START bit, waits for half a
bit time and samples the line again.

•    If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

•    The CPU reads the parallel data from the buffer register.

•    When the input register loads a parallel data to buffer register, the RxRDY line goes high.

•    The clock signal RxC (low) controls the rate at which bits are received by the USART.

•    During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

•    During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

•    The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

•    This unit takes care of handshake signals for MODEM interface.

MAXIMUM MODE CONFIGURATION OF 8086 SYSTEM

• If the MN/MX (low) pin is low i.e. zero, then the 8086 can operate in maximum mode.

• In this mode, the Bus controller (8288) chip used to generate control signals I/O W, I/O R, RD., WR (Active low), etc., by receiving the active low status signals (S2, S1 & S0) from the microprocessor.

• MRDC (low) : Memory read command – It instructs the memory to put the contents of the addressed location to the data bus.

• MWTC (low) : Memory write command – It instructs the memory to accept the data on the data bus and load that data into the address memory location.

• IORC (low) : I/O read command – It instructs an I/O device to put the data contained in the addressed port on the data bus.

• IOWC (low) : I/O write command – It instructs an I/O device to accept the data on the data bus and load the data into the addressed port.

• AIOWC (low) / AMWC (low) : Advance IO write command / Advance memory write command – These are similar to IOWC and MWTC except that they are activated one clock pulse earlier. This gives slow interfaces an extra clock cycle to prepare to input the data.

• This system also consists of latches, tristate buffer, memory input-output device, etc.

• The DEN, DT/R, ALE, etc is derived by the bus controller from the information available on the active low status signals (S2, S1 & S0).

• In this mode, Request/Grant pin (RQ/GT) is checked at each rising pulse of clock I/P when the request is detected and if Hold request are satisfied, the processor issues a grant pulse over RQ/GT pin immediately during T4 or next T1 state to accept the control of the bus. Therefore, the requesting controller uses the bus till it requires.

• When it is ready to relinquish the bus, it sends a release pulse to the processor using the RQ/GT pin.

The figure shows maximum mode 8086 systems.

Maximum mode of 8086

MINIMUM MODE CONFIGURATION OF 8086 SYSTEM

• When MN/MX (low) pin is in logic 1, the 8086 microprocessor operates in minimum mode system.

• In this mode, the microprocessor chip itself gives out all the control signals.

• This is a single processor mode.

• The remaining components in the system are latches, trans receivers, clock generator, memory or I/O devices.

• This system has three address latches and two octal data buffers for the complete 20-bit address and 16 bit data Separation.

• The latches are used for separating the valid address from the multiplexed address/data signals and the controlled by the ALE signal generated by 8086.

• Transceivers are the bi-directional buffers. They are required to separate the valid data from the time multiplexed address/data signal. This is controlled by two signals, DEN & DT/R (low).

• DT/R (low) indicates that the direction of data, iei.e. from or to the indicator.

• DEN signal indicates the valid data is available on the data bus.

• This system contains memory for the monitor and users program storage. It also contains I/O devices to communicate with the processor.

• The clock generator in the system is used to generate the clock and to synchronize some external signals with the system clock.

• The minimum mode system organization is,

Minimum mode of 8086

8086 PIN CONFIGURATION

• The 16-bit 8086 microprocessor has 40 pins.
• It is available in 5 MH, 8MHz and 10 MHz.
• It can operate in two modes, i.e. single processor (minimum mode) or multiprocessor moth (maximum mode) configuration.
• The signals are categorized in three groups as follows

(i) Common signal, which are used in minimum as well as maximum mode
(ii) Signal for minimum mode
(iii) Signals for maximum mode.

• The pin diagram for 8086 processor is shown in fig.

• The signals common for both maximum & minimum modes are:

Pin From 24 to 31 in Minimum Mode:

INTA (Interrupt Acknowledge) Output: This indicates recognition of an interrupt request.

HOLD input, HLDA output:

• A HIGH on HOLD pin indicates that another master (DMA) is requesting to take over the system bus.
• On receiving HOLD signal processor outputs HLDA signal HIGH as an acknowledgment.
• At the same time, processor tristates the system bus.
• A low on HOLD gives the system bus control back to the processor. Processor then outputs low signal on HLDA.

Pin Definitions (24 to 31) In Maximum Mode: