Registers Of 8051/8031 Microcontroller

 Timer Control Register (TCON):

•    The TCON register consists of timer overflow flags, timer run control bits, external interrupt flags and external interrupt type control bits.
•    The format of TCON register is,

•    When clock signal is applied, after reaching maximum value (i.e., the content of counter is all 1’s), the content of counter will become zero (i.e., all 0s). This condition is called timer overflow and this is also the end of timing maintain by using the timer.

•    The TCON register has a 1-bit flag, TF for each timer to indicate the timer overflow or end of timing.

•    Whenever the timer/counter overflows, the TF flag is set to one.

•    The TF flag is also used as an interrupt signal to initiate the execution of a subroutine. When the controller executes a subroutine, the TF flag is cleared.

•    The TR bit is used to start/stop the timer/counter. When TR bit is set to one, the timer/ counter will start counting and continue the counting as long as TR bit is one. The timer/counter will stop counting when TR bit is cleared to zero.

•    When a valid external interrupt signal is detected the IE flag is set to one. When the controller accepts the external interrupt and start processing it, the IE flag is cleared to zero.

•    The IT = 1, when it recognize falling edge triggered external interrupt and IT = 0, when it recognize logic low level external interrupt.


Interrupt Enable Register (IE):

•    The IE register is used to enable/disable the interrupts of 8051.

•    The interrupts are recognized by the controller only if they are enabled.

•    The format of IE register is,

•    If EA = 0, then it disable all the five interrupts of 8051.

•    If EA = 1, then it enable the interrupts. The EA bit is also called global enable.



Interrupt Priority Register (IP):

•    The 8051 has five interrupts.

•    The normal priority of these interrupts from highest to lowest are external interrupt-0, Timer-0 interrupt, External interrupt- 1, Timer-1 interrupt and serial Port interrupt.

•    The IP register can be programmed to make the priority of any of the interrupt as highest.

•    When the priority bit of a particular bit is programmed as one then its priority will be highest.

•    The format of IP register is,

Serial Port Control Register (SCON) Of 8051/8031 Microcontroller

•    The format of SCON register is shown.

•    Mode 0:

o    In this mode the serial port function as half duplex serial port with fixed baud rate.

o    The 8- bit serial data is received and transmitted through RxD pin and the controller output the shift clock through TxD pin during reception and transmission.

o    The baud rate is fixed at 1 / 12 of the oscillator frequency.

•    Mode 1:

o    In this mode the serial port function as full duplex serial port with variable baud rate.

o    In this mode one data consists of 10 bits, which includes one start bit, eight data bit and one stop bit. During reception the stop bit is stored as RB8 in SCON register.

o    Baud rate in mode-1 depends on the value of SMOD bit in PCON register and the timer-1overflow rate.

•    Mode 2:

o    In this mode the serial port function as full duplex serial port with a baud rate of either 1/32 or 1/64 of the oscillator frequency.

o    In this mode one data consists of 11 bits which includes one start bit, eight data bit, a programmable 9th data bit and one stop bit.

o    During transmission the TB8 of SCON register is added as 9th data bit and during reception the 9th data bit is stored as RB8 in SCON register.

o    The baud rate depends on the value of SMOD bit in PCON register.

•    Mode 3:

o    The mode-3 is same as mode-2, except the baud rate.

o     In mode-3, the baud rate is variable. The baud rate depends on the value of SMOD bit in PCON register and the timer- 1 overflow rate.

•       The serial mode bit-2 (SM2) has no effect in mode-0 and when programmed for mode-0, the SM2 should be equal to zero.


•    In mode-1, SM2 is used to check a valid stop bit during reception. In mode-1, if SM2 = 1, then receive interrupt (RI) is activated only when a valid stop bit is received.

•       In mode-2 and mode-3 the SM2 bit is used to enable multiprocessor communication.

•       In multiprocessor communication the serial port of a number of microcontrollers can be connected to a common serial bus. One controller will act as a master and all other controller will act as slave.

•       A unique 8-bit address is assigned to each slave and the SM2 bit in all the slaves is set to 1.

•       When SM2 bit is one, the slaves will consider the received byte as address and when SM2 bit is zero the slaves will consider the received byte as data.

•       For communication with a slave the master will first send as address byte and then a data byte.

•    The master initiates communication with a slave by sending the address of the slave on the bus. All the slaves will receive the address byte. Since SM2 = 1 initially in all the slaves, the received byte will be considered as address and the slaves will verify whether the received address matches with assigned address. The slave whose assigned address matches with received address will clear its SM2 bit. Now SM2 bit of only one of the slave will be zero.

•    Next the master will send a data byte which is also received by all the slave, but the data byte is accepted by the slave whose SM2 = 0 and so the receive interrupt is activated only in one of the slave whose SM2 = 0.

•    After reading the received data from SBUF register, the SM2 bit of the slave should be set to one again to receive next data.

•    The REN bit of SCON register can be used to enable or disable the serial reception. When REN = 1, the serial reception is enabled and when REN = 0, the serial reception is disabled.

•    The bits TI and RI of SCON register are transmitting interrupt flag and receive interrupt flag respectively.

•    The controller will set the TI bit during the transmission of stop bit of a data character in mode 1 to 3 and during the transmission 0 bit of a data character in mode-0.

•    The controller will set the RI bit during the reception of stop bit of a data character in mode 1 to 3 and during the reception of 8th bit of a data character in mode- 0.

Timer Mode Control Register (TMOD) Of 8051/8031 Microcontroller

•    The TMOD register is used to select the operating mode and the timer/counter operation of the timers.

•     The format of TMOD register is,

•    The lower four bits of TMOD register is used to control timer-0 and the upper four bits are used to control timer-1.

•    The two timers can be independently program to operate in various modes.

•    The TMOD register has two separate two bit field M0 and Ml to program the operating mode of timers. The operating modes of timers are mode-0, mode-1, mode-2 and mode-3. In all these operating modes the oscillator clock is divided by 12 and applied as input clock to timer.

MODE-0
o    In mode-0 the timer register is configured as 13-bit register.

o    For timer-1 the 8 bits of TH1 and lower 5 bits of TL1 are used to form 13-bit register.

o    For timer-0 the 8-bit of TH0 and lower 5 bits of TL0 are used to form 13-bit register.

o    The upper three bits of TL registers are ignored.

o     For every clock input to timer the 13-bit timer register is incremented by one When the timer count rolls over from all 1’s to all 0’s, (i.e., 1 1111 1111 1111 to 0 0000 0000 0000) the timer interrupt flag in TCON register is set to one.

Mode-1

o    The mode-1 is same as mode-0 except the size of the timer register. In mode-1 the TH and TL registers are cascaded to form 16-bit timer register.

MODE-2

o    In mode-2, the timers function as 8-bit timer with automatic reload feature. The TL register will function as 8-bit timer count register and the TH register will hold an initial count value.

o    When the timer is started, the initial value in TH is loaded to TL and for each clock input to timer the 8-bit timer count register is incremented by one.

o    When the timer count rolls over from all 1’s to all 0’s (i.e., 1111 1111 to 0000 0000), the timer interrupt flag in TCON register is set to one and the content of TH register is reloaded in TL register and the count process starts again from this initial value.

Mode-3

o    In mode-3, the timer-0 is configured as two separate 8-bit timers and the timer-1 is stopped.

o    In mode-3 the TL0 will function as 8-bit timer controlled by standard timer-0 control bits and the TH0 will function as 8-bit timer controlled by timer-1 control bits.

o    While timer-0 is programmed in mode-3, the timer-0 can be programmed in mode-0, 1 or 2 and can be used for an application that does not require an interrupt.

o    The C/T(Low) bit of TMOD register is used to program the counter or timer operation of the timer. When C/T bit is set to one, the timer will function as event counter. The C/T(Low) bit is programmed to zero for timer operation.

o    The timer will run only if clock input is allowed.

o    When GATE = 1, the clock input to timer is allowed only if the signal at pin is high and when GATE =0 the signal at INT (low) pin is ignored.