APPLICATIONS OF 8085 MICROPROCESSOR (DAC INTERFACE)

DAC  INTERFACE 

In many applications, the microprocessor has to produce analog signals for controlling certain analog devices. Basically the microprocessor system can produce only digital signals. In order to convert the digital signal to analog signal a Digital-to-Analog Converter. (DAC) has to be employed.

The DAC will accept a digital (binary) input and convert to analog voltage or current. Every DAC will have "n" input lines and an analog output.

The DAC require a reference analog voltage (Vref) or current (Iref) source.

The smallest possible analog value that can be represented by the n-bit binary code is called resolution. The resolution of DAC with n-bit binary input is 1/2n of reference analog value. Every analog output will be a multiple of the resolution. In some converters the input reference analog signal will be multiplied or divided by a constant to get full scale value. Now the resolution will be 1/2n of full scale value.

For example,
Consider an 8-bit DAC with reference analog voltage of 5 volts.
Now the resolution of the DAC is (1/28) x 5 volts.
The 8-bit digital input can take, 28 = 256 different values.
The analog values for all possible digital input are as shown in table below.

The maximum input digital signal will have an analog value which is equal to reference analog value minus resolution.

The digital-to-analog converters can be broadly classified into three categories, and they are

•    Current output
•    Voltage output 
•    Multiplying type

The current output DAC provides an analog current as output signal.
In voltage output DAC, the analog current signal is internally converted to voltage signal.

In multiplying type DAC, the output is given by the product of the input signal and the reference source and the product is linear over a broad range. Basically, there is not much difference between these three types and any DAC can be viewed as multiplying DAC.

Typical DAC circuit:

The basic components of a DAC are resistive network with appropriate values, switches, a reference source and a current to voltage converter as shown in figure below.

The switches in the circuit of figure above can be transistors which connects the resistance either to ground or Vref.  The resistors are connected in such a way that for any number of inputs, the total current is in binary proportion. The operational amplifier converts the current to a voltage signal V0, which can be calculated from the following equation. 

The circuit of figure shown above can be modified as 8-bitDAC, by increasing the number of R/2R ladder. For an 8-bit DAC the output voltage is given by

The time required for converting the digital signal to analog signal is called conversion time. It depends on the response time of the switching transistors and the output amplifier. If the DAC is interfaced to microprocessor then the digital data (Signal) should remain at the input of DAC, until the conversion is complete. Hence to hold the data a latch is provided at the input of DAC. 

The Digital-to-Analog converters compatible to microprocessors are available with or without internal latch and I to V converting amplifier. The AD558 of Analog Devices is an example of 8-bit DAC with an internal latch and I to V converting amplifiers. The output of AD558 is an analog voltage signal.     The AD558 can be directly interfaced to 8085 microprocessor bus and it requires only two control signals: Chip Select (CS) and Chip Enable (CE). [No handshake signals are necessary for interfacing a DAC. The time between loading two digital data to DAC is controlled by software time delay].

The DAC0808 of National Semiconductor Corporation is an example of 8-bit DAC without internal latch and I to V converting amplifier. The internal block diagram and the pin configuration of DAC0808 are shown in figure below.

The DAC0800 can be interfaced to 8085 system through an 8-bit latch as shown in figure below. The chip select (CS) signal from the decoder of the microprocessor system is delayed and inverted to clock the latch. If the DAC is memory mapped then the CS is from memory decoder. If the DAC is I/O mapped then CS is from I/O decoder. 

 

The processor sends an address, which is decoded by decoder in the microprocessor system to produce chip select signal. Then the processor sends a digital data to latch. The buffer and inverter will produce sufficient delay for CS signal so that, the latch is clocked only after the data is arrived at the input lines of the latch. When the latch is clocked the digital data is send to DAC. The DAC will produce a corresponding current signal, which is converted to voltage signal by the op-amp 741. The typical settling time of DAC0800 is 150nsec. Therefore the processor need not wait for loading next data.

INTERFACING 8259 WITH 8085 MICROPROCESSOR:

•    It requires two internal address and they are A =0 or A = 1.

•    It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085 is shown in figure is I/O mapped in the system.

•    The low order data bus lines D0-D7 are connected to D0-D7 of 8259.

•    The  address  line  A0  of the  8085  processor  is  connected  to  A0   of  8259  to  provide  the  internal address.

•    The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for
8259.

•    The address lines A4, A5  and A6  are used as input to decoder.

•    The control signal IO/M (low) is used as logic high enables for decoder and the address line A7  is used as logic low enable for decoder.

•    The I/O ad4ressès of 8259 are shown in table-8.5.

Working of 8259 with 8085 processor:

•    First  the  8259  should  be  programmed  by  sending  Initialization  Command  Word  (ICW)
and Operational Command Word (OCW). These command words will inform 8259 about the following,

* Type of interrupt signal (Level triggered / Edge triggered).

* Type of processor (8085/8086).

* Call address and its interval (4 or 8)

* Masking of interrupts.

* Priority of interrupts.

* Type of end of interrupts.

•    Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any one of the interrupt lines IR0-IR7  it checks for its priority and also checks whether it
is masked or not.

•    If  the  previous  interrupt  is  completed  and  if  the  current  request  has  highest  priority  and unmasked, then it is serviced.

•    For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085.

•    In response it expects an acknowledge INTA (low) from the processor.

•    When the processor accepts the interrupt, it sends three INTA (low) one by one.

•    In response to  first, second and third INTA (low) signals, the  8259 will supply CALL opcode, low byte of call address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and load the CALL address in PC and start executing the interrupt service routine stored in this call address.

Interfacing Intel 8251A with 8085 Processor

The 825 1A can be either memory mapped or I/O mapped in the system.

•    8251A in I/O mapped in the system is shown in the figure.

•    Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

•    The address lines A4, A5  and A6  are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 8251A.

•    The address line A7  and the control signal IO / M(low) are used as enable for decoder.

•    The address line  A0  of 8085 is connected to  C/D(low) of 8251A to provide the internal addresses.

•    The data lines D0  – D7  are connected to D0  – D7  of the processor to achieve parallel data transfer.

•    The RESET and clock signals are supplied by the processor. Here the processor clock is directly  connected  to  8251A.  This  clock  controls  the  parallel  data  transfer  between  the processor and 8251A.

•    The output clock signal of 8085 is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

•    The TTL logic levels of the serial data lines  and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then terminated on a standard 9-pin D-.type connector.

•    In 8251A the transmission and reception baud rates can be different or same.

•    The device which requires serial communication with processor can be connected to this
9-pin D-type connector using 9-core cable.

•    The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

•    I/O addresses of 8251A interfaced to 8085 is,

USART-INTEL 8251A MICROPROCESSOR

The  8251A  is  a  programmable  serial  communication  interface  chip  designed  for synchronous and asynchronous serial data communication.It supports the serial transmission of data.It is packed in a 28 pin DIP.

Pin Diagram of 8251A

Block Diagram:

The functional block diagram of 825 1A consists five sections. They are

•    Read/Write control logic
•    Transmitter
•    Receiver
•    Data bus buffer
•    Modem control.

  The functional block diagram is,

Functional block diagram of 8251A-USART

Read/Write control logic:

•    The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.

•    It monitors the data flow.

•    This  section  has  three  registers  and  they  are  control  register,  status  register  and  data buffer.

•    The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.

•    When C/D(low) is high, the control register is selected for writing control word or reading status word.

•    When C/D(low) is low, the data buffer is selected for read/write operation.

•    When the reset is high, it forces 8251A into the idle mode.

•    The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section:

•    The transmitter section accepts parallel data from CPU and converts them into serial data.

•    The  transmitter  section  is  double  buffered,  i.e.,  it  has  a  buffer  register  to  hold  an  8-bit parallel  data  and  another  register  called  output  register  to  convert  the  parallel  data  into
serial bits.

•    When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

•    If buffer register is empty, then TxRDY is goes to high.

•    If output register is empty then TxEMPTY goes to high.

•    The  clock  signal,  TxC  (low)  controls  the  rate  at  which  the  bits  are  transmitted  by  the
USART.

•    The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

•    The receiver section accepts serial data and convert them into parallel data.

•    The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

•    When the RxD line goes low, the control logic assumes it as a START bit, waits for half a
bit time and samples the line again.

•    If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

•    The CPU reads the parallel data from the buffer register.

•    When the input register loads a parallel data to buffer register, the RxRDY line goes high.

•    The clock signal RxC (low) controls the rate at which bits are received by the USART.

•    During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

•    During synchronous mode, the signal  SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

•    The MODEM control unit allows to interface  a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

•    This unit takes care of handshake signals for MODEM interface.