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MAXIMUM MODE CONFIGURATION OF 8086 SYSTEM

• If the MN/MX (low) pin is low i.e. zero, then the 8086 can operate in maximum mode.

• In this mode, the Bus controller (8288) chip used to generate control signals I/O W, I/O R, RD., WR (Active low), etc., by receiving the active low status signals (S2, S1 & S0) from the microprocessor.

• MRDC (low) : Memory read command – It instructs the memory to put the contents of the addressed location to the data bus.

• MWTC (low) : Memory write command – It instructs the memory to accept the data on the data bus and load that data into the address memory location.

• IORC (low) : I/O read command – It instructs an I/O device to put the data contained in the addressed port on the data bus.

• IOWC (low) : I/O write command – It instructs an I/O device to accept the data on the data bus and load the data into the addressed port.

• AIOWC (low) / AMWC (low) : Advance IO write command / Advance memory write command – These are similar to IOWC and MWTC except that they are activated one clock pulse earlier. This gives slow interfaces an extra clock cycle to prepare to input the data.

• This system also consists of latches, tristate buffer, memory input-output device, etc.

• The DEN, DT/R, ALE, etc is derived by the bus controller from the information available on the active low status signals (S2, S1 & S0).

• In this mode, Request/Grant pin (RQ/GT) is checked at each rising pulse of clock I/P when the request is detected and if Hold request are satisfied, the processor issues a grant pulse over RQ/GT pin immediately during T4 or next T1 state to accept the control of the bus. Therefore, the requesting controller uses the bus till it requires.

• When it is ready to relinquish the bus, it sends a release pulse to the processor using the RQ/GT pin.

The figure shows maximum mode 8086 systems.

Maximum mode of 8086

MINIMUM MODE CONFIGURATION OF 8086 SYSTEM

• When MN/MX (low) pin is in logic 1, the 8086 microprocessor operates in minimum mode system.

• In this mode, the microprocessor chip itself gives out all the control signals.

• This is a single processor mode.

• The remaining components in the system are latches, trans receivers, clock generator, memory or I/O devices.

• This system has three address latches and two octal data buffers for the complete 20-bit address and 16 bit data Separation.

• The latches are used for separating the valid address from the multiplexed address/data signals and the controlled by the ALE signal generated by 8086.

• Transceivers are the bi-directional buffers. They are required to separate the valid data from the time multiplexed address/data signal. This is controlled by two signals, DEN & DT/R (low).

• DT/R (low) indicates that the direction of data, iei.e. from or to the indicator.

• DEN signal indicates the valid data is available on the data bus.

• This system contains memory for the monitor and users program storage. It also contains I/O devices to communicate with the processor.

• The clock generator in the system is used to generate the clock and to synchronize some external signals with the system clock.

• The minimum mode system organization is,

Minimum mode of 8086

8086 PIN CONFIGURATION

• The 16-bit 8086 microprocessor has 40 pins.
• It is available in 5 MH, 8MHz and 10 MHz.
• It can operate in two modes, i.e. single processor (minimum mode) or multiprocessor moth (maximum mode) configuration.
• The signals are categorized in three groups as follows

(i) Common signal, which are used in minimum as well as maximum mode
(ii) Signal for minimum mode
(iii) Signals for maximum mode.

• The pin diagram for 8086 processor is shown in fig.

• The signals common for both maximum & minimum modes are:

Pin From 24 to 31 in Minimum Mode:

INTA (Interrupt Acknowledge) Output: This indicates recognition of an interrupt request.

HOLD input, HLDA output:

• A HIGH on HOLD pin indicates that another master (DMA) is requesting to take over the system bus.
• On receiving HOLD signal processor outputs HLDA signal HIGH as an acknowledgment.
• At the same time, processor tristates the system bus.
• A low on HOLD gives the system bus control back to the processor. Processor then outputs low signal on HLDA.

Pin Definitions (24 to 31) In Maximum Mode:

8086 – ARCHITECTURE

The 8086 processor is divided into two independent functional units. They are,

The bus interface unit (BIU).
The Execution Unit (EU).
These two units are linked using an internal data bus.


8086 Architecture

Bus Interface Unit:

•   The Bus interface unit (BIU) fetches instruction, reads data from memory and peripherals and writes data into memory and peripherals.

•   It contains segment registers, instruction pointer, instruction queue and address generation / bus control circuit to provide functions such as fetching and queuing of instruction and bus control.

•   The BIU’s instruction queue is a First In First Out (FIFO) group of registers in which up to six bytes of instruction code are projected from memory. This is done to speed up program execution by overlapping instruction fetch with execution. This mechanism is referred to as pipe lining.

•   If queue is full, the BIU does not perform any bus cycle i.e., BIU does not prefetch any instructions. Therefore, BIU may prefetch the instructions from memory until queue is full.

•   While fetching the instruction from memory, if the Execution Unit (EU) interrupts the BIU for memory access, the BIU first complete fetching and then services the EU.

•   If a subroutine call or Jump instructions are encountered, the BIU will reset the queue and begin refilling after passing the new instruction to the EU.

•   BIU contains an adder, which is used to produce the 20-bit address. The bus control logic of the BIU generates all the bus control signals such as read and write signals for memory and I/O.

•   It has four, 16 bit registers. These are

Code segment (CS) registers,
Data segment (DS) registers
Stack segment (SS) registers
Extra segment (ES) registers

• 8086 processor consists of I Mega Byte memory and is divided into segments of up to 64 Kbytes each.

Code segment (CS)

All program instructions must be located in main memory pointed to by the 16 bit CS register with a 16 bit offset in the segment contained in the 16 bit Instruction pointer. The BIU computes the 20 bit physical address.

Therefore the CS contains the start of the current code segment and IP contains the offset from this address to the next instruction byte to be fetched.

Eg : If CS = 456A16 and IP = 162016 , then the 20bit physical address is calculated by adding the IP with one position shifted value of CS.
20 bit address = 456A016 + 162016 = 46CC016

Stack segment (SS)

The SS register points to the current stack.

The 20-bit physical stack address is calculated from SS & SP for stack instructions.

The programmer can use the BP registers instead of SP for accessing the stack using the based addressing mode. In this case, the 20-bit physical stack address is calculated from SS & BP.

Data segment (DS)

The DS register points to current data segment, i.e. operands for most instructions are fetched from this segment.

The 16 bit contents of Source Index (SI) or Destination Index (DI) are used as offset for calculating the 20 bit physical address.

Extra segment (ES)

This register points to the extra segment, which excess data, is stored.

The DI is used as offset for calculating the 20-bit physical address. String instruction always uses ES and DI to calculate the 20-bit address for the destination.

Execution Unit:

• The EU decodes and executes instructions.

• A decoder in the EU, translates the instructions.

• It has a 16 bit ALU to perform arithmetic and logic operations.

• It has eight 16 bit registers (AX, BX, CX, DX, SP, BP, SI & DI).

• These 16 bit registers are used to store 16 bit/8 bit data.

• Each 16 bit register (AX, BX, CX, DX) is combination of two 8 bit register ie., AH (higher byte) and AL (lower byte) combines together to store a 16 bit data in (AX).

• AX acts as the 16 bit accumulator in which the Arithmetic & Logical operation are carried out.

• AL is the 8-bit accumulator.

• BX is the only general-purpose register, which is used for addressing 8086 memory.

• CX register is the counter register in which the contents always be decremented by 1.

• DX is the data register is used to hold excess 16 bit result while performing multiplication, division, etc.

• SP & BP are point registers, which are used to access data in stack segment. These are used as offset for SS.

• The EU also contains a 16-bit flag register which holds the status flags typically after an ALU operation.

• The flag register of 8086 micro processor is,

• The flags are divided into two classifications. They are,

(A) Condition code Flags

• These flags reflect the result of Operations Performed by ALU. They are,

Over flow flag (O): This flag is set, if an overflow occurs during the arithmetic operation of two signed numbers.

Sign flag (S): This flag is set, if an MSB of the accumulator is set after any computation.

Zero flag (Z): This flag is set, if the result of any computation is zero.

Auxiliary carry flag (AC): This flag is set, if there is a carry from the third bit, during addition or borrow.

Parity flag (P): The flag is set, if the lower byte result contains even number of 1’s.

Carry flag (CY): This flag is set, if any computation result contains a carry.

(B) Machine control flags

Direction Flag: This flag is set, if the string is processed from higher address towards lower address. Otherwise, the flag is reset. This is used only in string manipulation instructions.

Interrupt flag: This flag is set, only when maskable interrupts are recognized.

Trap flag: When a trap interrupt is received by the processor, this flag is set, which indicates, the processor to execute the current instruction and to transfer the control to trap service routine. In Other words, When 8086 enters in single step mode, this flag is set.

Features of 8086 Processor:

1.High speed of execution

2.More memory addressing capability

3.More powerful instruction set

4.16 bit data bus

5.20-bit address bus.

6.Computes 16 bit / 32 bit data.

7.Requires one +5V supply voltage

8.Require one clock phase of up to 5 MHz

9.It consists of 40 pin

Fluorescence Chemical Transducers

The knowledge of the partial pressure of oxygen (PO2), the pH, and the partial pressure of carbon dioxide (PCO2) in arterial blood is very important in the management of critically ill patients. Sensing elements with specific reagent chemistries for each of the above measurands are attached to the tips of each of three optical fibers. When used as intravascular transducers, the three fibers are enclosed in a single catheter which is then inserted into the artery through an incision for real-time continuous monitoring of the blood gases and pH. Light from a laser diode source at a specific wavelength enters the fiber at one end (proximal), propagates through the core, and irradiates the sensing element at the distal end inside the artery.

The sensing element contains a dye with fluorescent molecules which, on absorption of the photons, are excited to a higher-energy state. In that state, the molecule loses some of its energy to the lattice structure. As it returns with lower energy from an intermediate state of excitation, it fluoresces at a different wavelength.

Since the energy of a photon is inversely proportional to the wavelength, the energy in the emitted light is of a longer wavelength. The presence of an analyte (measurand) modifies the intensity of the reemitted (fluorescent) light. It can be measured using wavelength-selective devices and photonic detectors, whose output is proportional to the concentration of the measurand. An analyte such as oxygen quenches the fluorescence intensity.

This is the basic transduction mechanism in PO2 transducers. Based on the fluorescence quenching effect, intravascular PO2 transducers have been built as shown in Fig. 5.47a. The relationship between PO2 (measured) and the fluorescence characteristics of the dye molecule is given by the rearranged form of the Stern-Voltmer equation

where I is the fluorescence intensity after quenching by oxygen and I0 is the intensity in the absence of oxygen. K is the quenching constant, and it represents the slope of the PO2 vs. I0/I plot, which characterizes the performance of the oxygen transducer.108 By measuring I0 at the excitation wavelength and at the fluorescence wavelength , the partial pressure of oxygen can be determined.

The sensing element in a pH transducer is a pH-sensitive dye, whose acid from (HA) and the base form (A_) fluoresce at different excitation wavelengths, but the longer wavelength of fluorescence emission is the same for both forms,

Figure 5.47 Fiber-optic fluorescence chemical transducers. (a) Oxygen transducer based on the fluorescence quenching effect. (b) pH transducer.

as indicated in Fig. 5.47b.
This is the basic transduction mechanism. In this case, the pH can be expressed as

Physical Transducers

The most direct application of an optical fiber to measure physical measurands is the microbend transducer, as shown in Fig. 5.44.102,103,105 fiber is deformed by a measurand such as displacement, strain, pressure, force, acceleration, or temperature. In each case, the transduction mechanism is the decrease in light intensity of the beam through the fiber core as a result of the deformation, which causes the core modes to lose energy to the cladding modes. A photodetector is used to provide a corresponding electrical output. This is an intrinsic-type transducer.

Figure 5.45 shows a pressure transducer and a temperature transducer

Fig 5.45 Fiber-optic temperature and pressure transducers.

configured as a Fabry-Perot etalon or interferometer. The spacing between mirrors is critical to the operation of the etalon as a physical transducer.

Any change in that spacing, brought about by a measurand, will cause the transmittance of the etalon to change in proportion to the measurand. These extrinsic transducers are small in size and can be constructed by using integrated circuit techniques.

Optical fibers are also used to measure magnetic and acoustic fields. In a magnetic field transducer as shown in Fig. 5.46, the transduction mechanism consists of the longitudinal strain in the magnetostrictive material caused by the magnetic field and a corresponding strain in the core.

This strain modulates the refractive index of the core and produces a field-dependent phase shift in the output optical beam. An acoustic field transducer can also be made along these lines by replacing the magnetostrictive substrate with an acoustically sensitive coating around the fiber cladding. Consequently, this produces an acoustic field-dependent phase shift of the optical beam.