• In this mode, the Bus controller (8288) chip used to generate control signals I/O W, I/O R, RD., WR (Active low), etc., by receiving the active low status signals (S2, S1 & S0) from the microprocessor.
• MRDC (low) : Memory read command – It instructs the memory to put the contents of the addressed location to the data bus.
• MWTC (low) : Memory write command – It instructs the memory to accept the data on the data bus and load that data into the address memory location.
• IORC (low) : I/O read command – It instructs an I/O device to put the data contained in the addressed port on the data bus.
• IOWC (low) : I/O write command – It instructs an I/O device to accept the data on the data bus and load the data into the addressed port.
• AIOWC (low) / AMWC (low) : Advance IO write command / Advance memory write command – These are similar to IOWC and MWTC except that they are activated one clock pulse earlier. This gives slow interfaces an extra clock cycle to prepare to input the data.
• This system also consists of latches, tristate buffer, memory input-output device, etc.
• The DEN, DT/R, ALE, etc is derived by the bus controller from the information available on the active low status signals (S2, S1 & S0).
• In this mode, Request/Grant pin (RQ/GT) is checked at each rising pulse of clock I/P when the request is detected and if Hold request are satisfied, the processor issues a grant pulse over RQ/GT pin immediately during T4 or next T1 state to accept the control of the bus. Therefore, the requesting controller uses the bus till it requires.
• When it is ready to relinquish the bus, it sends a release pulse to the processor using the RQ/GT pin.
The figure shows maximum mode 8086 systems.
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| Maximum mode of 8086 |
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