The 8086 processor is divided into two independent functional units. They are,

  • The bus interface unit (BIU).
  • The Execution Unit (EU).
  • These two units are linked using an internal data bus.
8086 Architecture

Bus Interface Unit:

•    The Bus interface unit (BIU) fetches instruction, reads data from memory and peripherals and writes data into memory and peripherals.

•    It contains segment registers, instruction pointer, instruction queue and address generation / bus control circuit to provide functions such as fetching and queuing of instruction and bus control.

•    The BIU’s instruction queue is a First In First Out (FIFO) group of registers in which up to six bytes of instruction code are projected from memory. This is done to speed up program execution by overlapping instruction fetch with execution. This mechanism is referred to as pipe lining.

•    If queue is full, the BIU does not perform any bus cycle i.e., BIU does not prefetch any instructions. Therefore, BIU may prefetch the instructions from memory until queue is full.

•    While fetching the instruction from memory, if the Execution Unit (EU) interrupts the BIU for memory access, the BIU first complete fetching and then services the EU.

•    If a subroutine call or Jump instructions are encountered, the BIU will reset the queue and begin refilling after passing the new instruction to the EU.

•    BIU contains an adder, which is used to produce the 20-bit address. The bus control logic of the BIU generates all the bus control signals such as read and write signals for memory and I/O.

•    It has four, 16 bit registers. These are

  1.   Code segment (CS) registers,
  2.   Data segment (DS) registers
  3.   Stack segment (SS) registers
  4.   Extra segment (ES) registers

•    8086 processor consists of I Mega Byte memory and is divided into segments of up to 64 Kbytes each.
  •  Code segment (CS)
   All program instructions must be located in main memory pointed to by the 16 bit CS register with a 16 bit offset in the segment contained in the 16 bit Instruction pointer. The BIU computes the 20 bit physical address.

    Therefore the CS contains the start of the current code segment and IP contains the offset from this address to the next instruction byte to be fetched.
            Eg  :    If CS = 456A16  and  IP = 162016 , then the 20bit physical address is calculated by adding the IP with one position shifted value of CS.
            20 bit address = 456A016 + 162016 = 46CC016

  •  Stack segment (SS)
The SS register points to the current stack.

The 20-bit physical stack address is calculated from SS & SP for stack instructions.

The programmer can use the BP registers instead of SP for accessing the stack using the based addressing mode. In this case, the 20-bit physical stack address is calculated from SS & BP.

  •     Data segment (DS)
    The DS register points to current data segment, i.e. operands for most instructions are fetched from this segment.
    The 16 bit contents of Source Index (SI) or Destination Index (DI) are used as offset for calculating the 20 bit physical address.

  • Extra segment (ES)
This register points to the extra segment, which excess data, is stored.

The DI is used as offset for calculating the 20-bit physical address. String instruction always uses ES and DI to calculate the 20-bit address for the destination.

Execution Unit:

• The EU decodes and executes instructions.

• A decoder in the EU, translates the instructions.

• It has a 16 bit ALU to perform arithmetic and logic operations.

• It has eight 16 bit registers (AX, BX, CX, DX, SP, BP, SI & DI).

• These 16 bit registers are used to store 16 bit/8 bit data.

• Each 16 bit register (AX, BX, CX, DX) is combination of two 8 bit register ie., AH (higher byte) and AL (lower byte) combines together to store a 16 bit data in (AX).

• AX acts as the 16 bit accumulator in which the Arithmetic & Logical operation are carried out.

• AL is the 8-bit accumulator.

• BX is the only general-purpose register, which is used for addressing 8086 memory.

• CX register is the counter register in which the contents always be decremented by 1.

• DX is the data register is used to hold excess 16 bit result while performing multiplication, division, etc.

• SP & BP are point registers, which are used to access data in stack segment. These are used as offset for SS.

• The EU also contains a 16-bit flag register which holds the status flags typically after an ALU operation.

• The flag register of 8086 micro processor is,

• The flags are divided into two classifications. They are,

    (A) Condition code Flags

• These flags reflect the result of Operations Performed by ALU. They are,

Over flow flag (O):
This flag is set, if an overflow occurs during the arithmetic operation of two signed numbers.

Sign flag (S): This flag is set, if an MSB of the accumulator is set after any computation.

Zero flag (Z):
This flag is set, if the result of any computation is zero.

Auxiliary carry flag (AC): This flag is set, if there is a carry from the third bit, during addition or borrow.

Parity flag (P): The flag is set, if the lower byte result contains even number of 1’s.

Carry flag (CY):
This flag is set, if any computation result contains a carry.

       (B) Machine control flags

Direction Flag: This flag is set, if the string is processed from higher address towards lower address. Otherwise, the flag is reset. This is used only in string manipulation instructions.

Interrupt flag: This flag is set, only when maskable interrupts are recognized.

Trap flag: When a trap interrupt is received by the processor, this flag is set, which indicates, the processor to execute the current instruction and to transfer the control to trap service routine. In Other words, When 8086 enters in single step mode, this flag is set.

No comments:

Post a Comment


PROJECTS 8086 PIN CONFIGURATION 80X86 PROCESSORS TRANSDUCERS 8086 – ARCHITECTURE Hall-Effect Transducers INTEL 8085 OPTICAL MATERIALS BIPOLAR TRANSISTORS INTEL 8255 Optoelectronic Devices Thermistors thevenin's theorem MAXIMUM MODE CONFIGURATION OF 8086 SYSTEM ASSEMBLY LANGUAGE PROGRAMME OF 80X86 PROCESSORS POWER PLANT ENGINEERING PRIME MOVERS 8279 with 8085 MINIMUM MODE CONFIGURATION OF 8086 SYSTEM MISCELLANEOUS DEVICES MODERN ENGINEERING MATERIALS 8085 Processor- Q and A-1 BASIC CONCEPTS OF FLUID MECHANICS OSCILLATORS 8085 Processor- Q and A-2 Features of 8086 PUMPS AND TURBINES 8031/8051 MICROCONTROLLER Chemfet Transducers DIODES FIRST LAW OF THERMODYNAMICS METHOD OF STATEMENTS 8279 with 8086 HIGH VOLTAGE ENGINEERING OVERVOLATGES AND INSULATION COORDINATION Thermocouples 8251A to 8086 ARCHITECTURE OF 8031/8051 Angle-Beam Transducers DATA TRANSFER INSTRUCTIONS IN 8051/8031 INSTRUCTION SET FOR 8051/8031 INTEL 8279 KEYBOARD AND DISPLAY INTERFACES USING 8279 LOGICAL INSTRUCTIONS FOR 8051/8031 Photonic Transducers TECHNOLOGICAL TIPS THREE POINT STARTER 8257 with 8085 ARITHMETIC INSTRUCTIONS IN 8051/8031 LIGHTNING PHENOMENA Photoelectric Detectors Physical Strain Gage Transducers 8259 PROCESSOR APPLICATIONS OF HALL EFFECT BRANCHING INSTRUCTIONS FOR 8051/8031 CPU OF 8031/8051 Capacitive Transducers DECODER Electromagnetic Transducer Hall voltage INTEL 8051 MICROCONTROLLER INTEL 8251A Insulation Resistance Test PINS AND SIGNALS OF 8031/8051 Physical Transducers Resistive Transducer STARTERS Thermocouple Vacuum Gages USART-INTEL 8251A APPLICATIONs OF 8085 MICROPROCESSOR CAPACITANCE Data Transfer Instructions In 8086 Processors EARTH FAULT RELAY ELECTRIC MOTORS ELECTRICAL AND ELECTRONIC INSTRUMENTS ELECTRICAL BREAKDOWN IN GASES FIELD EFFECT TRANSISTOR (FET) INTEL 8257 IONIZATION AND DECAY PROCESSES Inductive Transducers Microprocessor and Microcontroller OVER CURRENT RELAY OVER CURRENT RELAY TESTING METHODS PhotoConductive Detectors PhotoVoltaic Detectors Registers Of 8051/8031 Microcontroller Testing Methods ADC INTERFACE AMPLIFIERS APPLICATIONS OF 8259 EARTH ELECTRODE RESISTANCE MEASUREMENT TESTING METHODS EARTH FAULT RELAY TESTING METHODS Electricity Ferrodynamic Wattmeter Fiber-Optic Transducers IC TESTER IC TESTER part-2 INTERRUPTS Intravascular imaging transducer LIGHTNING ARRESTERS MEASUREMENT SYSTEM Mechanical imaging transducers Mesh Current-2 Millman's Theorem NEGATIVE FEEDBACK Norton's Polarity Test Potentiometric transducers Ratio Test SERIAL DATA COMMUNICATION SFR OF 8051/8031 SOLIDS AND LIQUIDS Speed Control System 8085 Stepper Motor Control System Winding Resistance Test 20 MVA 6-digits 6-digits 7-segment LEDs 7-segment A-to-D A/D ADC ADVANTAGES OF CORONA ALTERNATOR BY POTIER & ASA METHOD ANALOG TO DIGITAL CONVERTER AUXILIARY TRANSFORMER AUXILIARY TRANSFORMER TESTING AUXILIARY TRANSFORMER TESTING METHODS Analog Devices A–D BERNOULLI’S PRINCIPLE BUS BAR BUS BAR TESTING Basic measuring circuits Bernoulli's Equation Bit Manipulation Instruction Buchholz relay test CORONA POWER LOSS CURRENT TRANSFORMER CURRENT TRANSFORMER TESTING Contact resistance test Current to voltage converter DAC INTERFACE DESCRIBE MULTIPLY-EXCITED Digital Storage Oscilloscope Display Driver Circuit E PROMER ELPLUS NT-111 EPROM AND STATIC RAM EXCITED MAGNETIC FIELD Electrical Machines II- Exp NO.1 Energy Meters FACTORS AFFECTING CORONA FLIP FLOPS Fluid Dynamics and Bernoulli's Equation Fluorescence Chemical Transducers Foil Strain Gages HALL EFFECT HIGH VOLTAGE ENGG HV test HYSTERESIS MOTOR Hall co-efficient Hall voltage and Hall Co-efficient High Voltage Insulator Coating Hot-wire anemometer How to Read a Capacitor? IC TESTER part-1 INSTRUMENT TRANSFORMERS Importance of Hall Effect Insulation resistance check Insulator Coating Knee point Test LEDs LEDs Display Driver LEDs Display Driver Circuit LM35 LOGIC CONTROLLER LPT LPT PORT LPT PORT EXPANDER LPT PORT LPT PORT EXTENDER Life Gone? MAGNETIC FIELD MAGNETIC FIELD SYSTEMS METHOD OF STATEMENT FOR TRANSFORMER STABILITY TEST METHODS OF REDUCING CORONA EFFECT MULTIPLY-EXCITED MULTIPLY-EXCITED MAGNETIC FIELD SYSTEMS Mesh Current Mesh Current-1 Moving Iron Instruments Multiplexing Network Theorems Node Voltage Method On-No Load And On Load Condition PLC PORT EXTENDER POTIER & ASA METHOD POWER TRANSFORMER POWER TRANSFORMER TESTING POWER TRANSFORMER TESTING METHODS PROGRAMMABLE LOGIC PROGRAMMABLE LOGIC CONTROLLER Parallel Port EXPANDER Paschen's law Piezoelectric Wave-Propagation Transducers Potential Transformer RADIO INTERFERENCE RECTIFIERS REGULATION OF ALTERNATOR REGULATION OF THREE PHASE ALTERNATOR Read a Capacitor SINGLY-EXCITED SOLIDS AND LIQUIDS Classical gas laws Secondary effects Semiconductor strain gages Speaker Driver Strain Gages Streamer theory Superposition Superposition theorem Swinburne’s Test TMOD TRANSFORMER TESTING METHODS Tape Recorder Three-Phase Wattmeter Transformer Tap Changer Transformer Testing Vector group test Virus Activity Voltage Insulator Coating Voltage To Frequency Converter Voltage to current converter What is analog-to-digital conversion Windows work for Nokia capacitor labels excitation current test magnetic balance voltage to frequency converter wiki electronic frequency converter testing voltage with a multimeter 50 hz voltages voltmeter

Search More Posts