The 8086 processor is divided into two independent functional units. They are,
• The Bus interface unit (BIU) fetches instruction, reads data from memory and peripherals and writes data into memory and peripherals.
• It contains segment registers, instruction pointer, instruction queue and address generation / bus control circuit to provide functions such as fetching and queuing of instruction and bus control.
• The BIU’s instruction queue is a First In First Out (FIFO) group of registers in which up to six bytes of instruction code are projected from memory. This is done to speed up program execution by overlapping instruction fetch with execution. This mechanism is referred to as pipe lining.
• If queue is full, the BIU does not perform any bus cycle i.e., BIU does not prefetch any instructions. Therefore, BIU may prefetch the instructions from memory until queue is full.
• While fetching the instruction from memory, if the Execution Unit (EU) interrupts the BIU for memory access, the BIU first complete fetching and then services the EU.
• If a subroutine call or Jump instructions are encountered, the BIU will reset the queue and begin refilling after passing the new instruction to the EU.
• BIU contains an adder, which is used to produce the 20-bit address. The bus control logic of the BIU generates all the bus control signals such as read and write signals for memory and I/O.
• It has four, 16 bit registers. These are
• 8086 processor consists of I Mega Byte memory and is divided into segments of up to 64 Kbytes each.
Therefore the CS contains the start of the current code segment and IP contains the offset from this address to the next instruction byte to be fetched.
The 20-bit physical stack address is calculated from SS & SP for stack instructions.
The programmer can use the BP registers instead of SP for accessing the stack using the based addressing mode. In this case, the 20-bit physical stack address is calculated from SS & BP.
The DI is used as offset for calculating the 20-bit physical address. String instruction always uses ES and DI to calculate the 20-bit address for the destination.
Execution Unit:
• The EU decodes and executes instructions.
• A decoder in the EU, translates the instructions.
• It has a 16 bit ALU to perform arithmetic and logic operations.
• It has eight 16 bit registers (AX, BX, CX, DX, SP, BP, SI & DI).
• These 16 bit registers are used to store 16 bit/8 bit data.
• Each 16 bit register (AX, BX, CX, DX) is combination of two 8 bit register ie., AH (higher byte) and AL (lower byte) combines together to store a 16 bit data in (AX).
• AX acts as the 16 bit accumulator in which the Arithmetic & Logical operation are carried out.
• AL is the 8-bit accumulator.
• BX is the only general-purpose register, which is used for addressing 8086 memory.
• CX register is the counter register in which the contents always be decremented by 1.
• DX is the data register is used to hold excess 16 bit result while performing multiplication, division, etc.
• SP & BP are point registers, which are used to access data in stack segment. These are used as offset for SS.
• The EU also contains a 16-bit flag register which holds the status flags typically after an ALU operation.
• The flag register of 8086 micro processor is,
• The flags are divided into two classifications. They are,
(A) Condition code Flags
• These flags reflect the result of Operations Performed by ALU. They are,
Over flow flag (O): This flag is set, if an overflow occurs during the arithmetic operation of two signed numbers.
Sign flag (S): This flag is set, if an MSB of the accumulator is set after any computation.
Zero flag (Z): This flag is set, if the result of any computation is zero.
Auxiliary carry flag (AC): This flag is set, if there is a carry from the third bit, during addition or borrow.
Parity flag (P): The flag is set, if the lower byte result contains even number of 1’s.
Carry flag (CY): This flag is set, if any computation result contains a carry.
(B) Machine control flags
Direction Flag: This flag is set, if the string is processed from higher address towards lower address. Otherwise, the flag is reset. This is used only in string manipulation instructions.
Interrupt flag: This flag is set, only when maskable interrupts are recognized.
Trap flag: When a trap interrupt is received by the processor, this flag is set, which indicates, the processor to execute the current instruction and to transfer the control to trap service routine. In Other words, When 8086 enters in single step mode, this flag is set.
- The bus interface unit (BIU).
- The Execution Unit (EU).
- These two units are linked using an internal data bus.
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| 8086 Architecture |
Bus Interface Unit:
• The Bus interface unit (BIU) fetches instruction, reads data from memory and peripherals and writes data into memory and peripherals.
• It contains segment registers, instruction pointer, instruction queue and address generation / bus control circuit to provide functions such as fetching and queuing of instruction and bus control.
• The BIU’s instruction queue is a First In First Out (FIFO) group of registers in which up to six bytes of instruction code are projected from memory. This is done to speed up program execution by overlapping instruction fetch with execution. This mechanism is referred to as pipe lining.
• If queue is full, the BIU does not perform any bus cycle i.e., BIU does not prefetch any instructions. Therefore, BIU may prefetch the instructions from memory until queue is full.
• While fetching the instruction from memory, if the Execution Unit (EU) interrupts the BIU for memory access, the BIU first complete fetching and then services the EU.
• If a subroutine call or Jump instructions are encountered, the BIU will reset the queue and begin refilling after passing the new instruction to the EU.
• BIU contains an adder, which is used to produce the 20-bit address. The bus control logic of the BIU generates all the bus control signals such as read and write signals for memory and I/O.
• It has four, 16 bit registers. These are
- Code segment (CS) registers,
- Data segment (DS) registers
- Stack segment (SS) registers
- Extra segment (ES) registers
• 8086 processor consists of I Mega Byte memory and is divided into segments of up to 64 Kbytes each.
- Code segment (CS)
All program instructions must be located in main memory pointed to by the 16 bit CS register with a 16 bit offset in the segment contained in the 16 bit Instruction pointer. The BIU computes the 20 bit physical address.
Therefore the CS contains the start of the current code segment and IP contains the offset from this address to the next instruction byte to be fetched.
Eg : If CS = 456A16 and IP = 162016 , then the 20bit physical address is calculated by adding the IP with one position shifted value of CS.
20 bit address = 456A016 + 162016 = 46CC016
20 bit address = 456A016 + 162016 = 46CC016
- Stack segment (SS)
The 20-bit physical stack address is calculated from SS & SP for stack instructions.
The programmer can use the BP registers instead of SP for accessing the stack using the based addressing mode. In this case, the 20-bit physical stack address is calculated from SS & BP.
- Data segment (DS)
The DS register points to current data segment, i.e. operands for most instructions are fetched from this segment.
The 16 bit contents of Source Index (SI) or Destination Index (DI) are used as offset for calculating the 20 bit physical address.
- Extra segment (ES)
The DI is used as offset for calculating the 20-bit physical address. String instruction always uses ES and DI to calculate the 20-bit address for the destination.
Execution Unit:
• The EU decodes and executes instructions.
• A decoder in the EU, translates the instructions.
• It has a 16 bit ALU to perform arithmetic and logic operations.
• It has eight 16 bit registers (AX, BX, CX, DX, SP, BP, SI & DI).
• These 16 bit registers are used to store 16 bit/8 bit data.
• Each 16 bit register (AX, BX, CX, DX) is combination of two 8 bit register ie., AH (higher byte) and AL (lower byte) combines together to store a 16 bit data in (AX).
• AX acts as the 16 bit accumulator in which the Arithmetic & Logical operation are carried out.
• AL is the 8-bit accumulator.
• BX is the only general-purpose register, which is used for addressing 8086 memory.
• CX register is the counter register in which the contents always be decremented by 1.
• DX is the data register is used to hold excess 16 bit result while performing multiplication, division, etc.
• SP & BP are point registers, which are used to access data in stack segment. These are used as offset for SS.
• The EU also contains a 16-bit flag register which holds the status flags typically after an ALU operation.
• The flag register of 8086 micro processor is,
(A) Condition code Flags
• These flags reflect the result of Operations Performed by ALU. They are,
Over flow flag (O): This flag is set, if an overflow occurs during the arithmetic operation of two signed numbers.
Sign flag (S): This flag is set, if an MSB of the accumulator is set after any computation.
Zero flag (Z): This flag is set, if the result of any computation is zero.
Auxiliary carry flag (AC): This flag is set, if there is a carry from the third bit, during addition or borrow.
Parity flag (P): The flag is set, if the lower byte result contains even number of 1’s.
Carry flag (CY): This flag is set, if any computation result contains a carry.
(B) Machine control flags
Direction Flag: This flag is set, if the string is processed from higher address towards lower address. Otherwise, the flag is reset. This is used only in string manipulation instructions.
Interrupt flag: This flag is set, only when maskable interrupts are recognized.
Trap flag: When a trap interrupt is received by the processor, this flag is set, which indicates, the processor to execute the current instruction and to transfer the control to trap service routine. In Other words, When 8086 enters in single step mode, this flag is set.
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