The IC 2764 is selected for EPROM memory and the IC 6264 is selected for RAM memory.
Both the memory lC have time compatibility with 8085 processor.
The 8kb EPROM, 2764 require 13 address tines. The 8kb RAM, 6264 require 13 address lines.
The address lines A0 to A12 are connected to both EPROM and RAM memory ICs.
The 8255 require four internal addresses.
Let us connect A1 of 8085 to A0 of 8255 and A2 of 8085 to A1 of 8255.
The 8255 is memory mapped in the system.
For the memories and 8255’ s we require 5 chip-select signals. Hence we can use a 3-to-8 decoder 74LS138 for generating eight chip-select signals by decoding the unused address lines A13, A14 and A15.
The decoder enable pins are permanently tied to appropriate levels. In the eight chips select
signals five are used for selecting memory ICs and 8255, and the remaining three can be used for future expansion.
The EPROM is mapped at the starting of memory space. The RAM is mapped at the end of memory space. The EPROM is mapped from 0000H to IFFFH. The RAM is mapped from E000H to FFFFH.
The four internal devices of 8255 are control register, port-A, port-B and port-C. A 16-bit address is allotted to each internal device of 8255.
Both the memory lC have time compatibility with 8085 processor.
The 8kb EPROM, 2764 require 13 address tines. The 8kb RAM, 6264 require 13 address lines.
The address lines A0 to A12 are connected to both EPROM and RAM memory ICs.
The 8255 require four internal addresses.
Let us connect A1 of 8085 to A0 of 8255 and A2 of 8085 to A1 of 8255.
The 8255 is memory mapped in the system.
For the memories and 8255’ s we require 5 chip-select signals. Hence we can use a 3-to-8 decoder 74LS138 for generating eight chip-select signals by decoding the unused address lines A13, A14 and A15.
The decoder enable pins are permanently tied to appropriate levels. In the eight chips select
signals five are used for selecting memory ICs and 8255, and the remaining three can be used for future expansion.
The EPROM is mapped at the starting of memory space. The RAM is mapped at the end of memory space. The EPROM is mapped from 0000H to IFFFH. The RAM is mapped from E000H to FFFFH.
The four internal devices of 8255 are control register, port-A, port-B and port-C. A 16-bit address is allotted to each internal device of 8255.
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| Memory and I/O Port Interfacing with 8085 |
The 16 bit address for the memory and 8255 devices are,
A system requires 16kb EPROM and 16kb RAM. Also the system has 2 numbers of 8255, one number of 8279, one number of 8251 and one number of 8254. (8255 - Programmable peripheral interface; 8279-Keyboard/display controller, 8251 – USART and 8254 - Timer). Draw the Interface diagram. Allocate addresses to all the devices. The peripheral IC should be I/O mapped.
• The I/O devices in the system should be mapped by standard I/O mapping. Hence separate decoders can be used to generate chip select signals for memory IC and peripheral IC’ s.
• For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
• For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
• The 8kb memories require 13 address lines. Hence the address lines A0 – A12 are used for selecting the memory locations.
• The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-to-8-deeoder)
of memory IC. The logic low enables of this decoder are tied to IO/ M(low) of 8085, so that this decoder is enabled for memory read/write operation. The other enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of the decoder are used to select memory lCs and
the remaining 4 are kept for future expansion.
• The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
• The RAM is mapped at the end of memory space from C000 to FFFFH.
• There are five peripheral IC’ s to be interfaced to the system. The chip-select signals for these IC’ s
are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to this decoder is A11, A12 and A13
• The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O decoder.
• The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this decoder is enabled for I/O read/write operation.
• The I/O devices in the system should be mapped by standard I/O mapping. Hence separate decoders can be used to generate chip select signals for memory IC and peripheral IC’ s.
• For 16kb EPROM, we can provide 2 numbers of 2764(8k x 8) EPROM.
• For 16kb RAM we can provide 2 numbers of 6264 (8k x 8) RAM.
• The 8kb memories require 13 address lines. Hence the address lines A0 – A12 are used for selecting the memory locations.
• The unused address lines A13, A14 and A15 are used as input to decoder 74LS138 (3-to-8-deeoder)
of memory IC. The logic low enables of this decoder are tied to IO/ M(low) of 8085, so that this decoder is enabled for memory read/write operation. The other enable pins of decoder are tied to appropriate logic levels permanently. The 4-outputs of the decoder are used to select memory lCs and
the remaining 4 are kept for future expansion.
• The EPROM is mapped in the beginning of memory space from 0000H to 3FFF.
• The RAM is mapped at the end of memory space from C000 to FFFFH.
• There are five peripheral IC’ s to be interfaced to the system. The chip-select signals for these IC’ s
are given through another 3-to-8 decoder 74LS138 (I/O decoder). The input to this decoder is A11, A12 and A13
• The address lines A13, A14 and A15 are logically ORed and applied to low enable of I/O decoder.
• The logic high enable of I/O decoder is tied to IO / M(low) signal of 8085, so that this decoder is enabled for I/O read/write operation.
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| Memory and I/O Port Interfacing with 8085 |
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