INPUT/OUTPUT PINS, PORTS & CIRCUITS OF 8051/8031 MICROCONTROLLER

•    The 8051 has 32 I/O pins configured as four eight-bit parallel ports (P0, P1, P2, and P3).

•    All four ports are bi-directional.

•    Each port consists of a latch, an output driver, and an input buffer.

•    The output drives of Ports 0 and 2 and the input buffers of Port 0, are used in access to external memory.

•    Port 0 outputs the low order byte of the external memory address, time multiplexed with the data being written or read.

•    Port 2 outputs the high order byte of the external memory address when the address is 16 bits wide. Otherwise Port 2 gives the contents of special function register.

•    All port pins of Port 3 are multifunctional.

•    They have special functions including two external interrupts, two counter inputs, two special data lines and two timing control strobes.

P3-Alternate Special Function of port3

I/O Configuration:

Port 0 bit

Port 0 bit

Port 2 bit

Port 3 bit

•    The bit latch is nothing but the one bit in the port’s SFR. It is represented as a D flip-flop.

•    “Write to latch” acts as clock input for D flip-flop. The data from the internal bus is clock-in in response to a “write to latch” signal from the CPU. The Q (active low) output or Q output after inversion from D flip-flop is connected at the gate input of the drive FET.

•    The On and OFF state of the drive FET due to the data available at the output of latch decides the status of the output pin.

•     It is possible to read Q output of latch by activating “read latch” signal from the CPU.

•    The actual port status can he read by activating “read pin” signal.

•    For Port 0 and Port 2 drivers are switchable to internal ADDR/DATA and ADDR bus, respectively, by internal CONTROL signal.

•    The switching is required to access external memory. During external memory accesses, the P2 SFR remains unchanged, but P0 SFR gets 1s written to it.

•    Port 3 has multifunction pins. Therefore, each pin of Port 3 can be programmed to use as I/O or as one of the alternate function. This is achieved by another control input, “Alternate output function’.

•    When latch bit of Port 3 contains 1, the output level is controlled by control input, “alternate output function.”

•    The port pin can be configured as an input by writing 1 in the latch bit of the corresponding pin. It turns OFF the output driver FET. Then for, Ports 1,2 and 3, the pin is pulled high by the internal pull-up, but can be pulled low by an external source. There is no internal pull-up for port 0. Therefore, its output pin floats when 1 is written in the latch bit, and pin can be used as a high impedance input.

•     The port 0 is said to be “true bidirectional”, because when configured as an input it floats.

•    The output of Ports 1, 2 and 3 are pulled high with pull-up registers, when configured as an input. Thus they are sometimes called “quasi bidirectional” ports.

MEMORY INTERFACING OF Of 8051/8031 MICROCONTROLLER

Q.) An 8031 microcontroller based system requires 8kb program memory and 8kb external data memory. Also it requires 8279 for keyboard/display interface and 8255 for additional I/O ports. Develop a schematic to interface the memories, 8279 and 8255 to 8031 microcontroller, and allocate addresses to all the devices.

•    The 8kb program memory can be provided by using one number of 8kb EPROM 2764. The 8kb EPROM require 13 address lines and so the address lines A0 – A12 are connected to EPROM address pins to select its internal locations.

•    The remaining address lines A13, A14 and A15 are logically ORed and used as chip select signal for EPROM.

•    The signal PSEN(low) is used as read control signal for EPROM and so the EPROM can be accessed only as program memory. Here the EPROM is mapped in the first 8kb of program memory address space with address range 0000H to 1FFFH. (Here the remaining 56kb program memory address space is not utilized).

•    The 8031 provide a separate 64kb external data memory address space.

•    The RAM memory, 8279 and 8255 can be interfaced to 8031 as data memory

•    The 8kb RAM can be provided by using one number of 8kb RAM 6264. The 8kb RAM requires 13 address lines and so the address lines A0 – A12 are connected to address pins of RAM to select its internal location.

•    The 8255 require two address lines to select its internal devices port-A, port-B, port-C and control register. Hence the address lines A0 and A1 of controller are connected to A0 and A1 of 8255 respectively.

•    The 8279 require one address line to select its data register and control register. Hence the address line A0 of 8031 is connected to A0 of 8279.

•    A 2-to-4 decoder is employed in the system to generate the chip select signals required for the RAM, 8255 and 8279. The address lines A13 and A14 are connected to input of decoder to generate four chip select signals. The address line A15 is used as logic low chip enable for decoder.

•    In 8031 based system, the pin of 8031 is permanently grounded.

•    The 8031 provides separate read and write control signals RD(low) and WR(low) for reading and writing with devices interfaced as data memory.

•    The 8031 has a separate 256 bytes internal data memory address space allotted to internal RAM and SFR.

Address allocation for interfacing of 8031

Q.) An 8051 microcontroller based systems require 32 kb program memory and 16kb data memory. The system should also utilize the internal 4kb RAM. Also the system should include a keyboard/display controller 8279 and an 8255 I/O port device. Draw the interface diagram and allocate addresses to memory and I/O devices.

•    The 8051 has 4kb internal ROM which is mapped in the beginning of program memory address space with address in the range 0000H to 0FFFH.

•    Hence for a total requirement of 32kb, we have to provide 28kb external memory. Therefore one number 32kb EPROM 27256 can be interfaced to microcontroller in which the first 4kb will not be accessed by the controller if pin EA(low) is tied to Vcc or +5V.

•    The 32kb EPROM require 15 address lines and so the address lines A0 to A14 are connected to the address pins of EPROM to select its internal locations.

•    The address line A15 is used as chip s signal.

•    The EPROM is selected for program memory addresses when A0 = 0.

•    The signal PSEN(low) is used as read control signal for EPROM and so the EPROM can be
             accessed only as program memory.   

•    The 16kb RAM memory can be implemented by using two numbers of 8kb RAM 6264.

•    The RAM memories, 8255 and 8279 can be interfaced to 8051 controllers as data memory.

•    The 8kb RAM require 13 address lines and so the address lines A0 – A12 are connected to address pins of RAM to select its internal locations.

•    The address line A0 and A1 are connected to 8255 and the address line A0 is connected to 8279 to select their internal devices.

•    A 2-to-4 decoder is employed in the system to generate the chip select signals required for RAM, 8255 and 8279. The address lines A13 and A14 are connected to input of decoder to generate four chip select signals. The address line A15 is used as logic low chip enable for decoder.

•    Since the internal ROM is used in the system, the pin EA(low) should be tied to Vcc or +5V.

•    The 8051 provides separate read and write control signals RD(low) and WR(low) for reading and writing with devices interfaced as data memory.

•    The 8051 has a separate 256 bytes internal data memory address space allotted to internal RAM and SFR.