• All four ports are bi-directional.
• Each port consists of a latch, an output driver, and an input buffer.
• The output drives of Ports 0 and 2 and the input buffers of Port 0, are used in access to external memory.
• Port 0 outputs the low order byte of the external memory address, time multiplexed with the data being written or read.
• Port 2 outputs the high order byte of the external memory address when the address is 16 bits wide. Otherwise Port 2 gives the contents of special function register.
• All port pins of Port 3 are multifunctional.
• They have special functions including two external interrupts, two counter inputs, two special data lines and two timing control strobes.
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| P3-Alternate Special Function of port3 |
I/O Configuration:
Port 0 bit
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| Port 0 bit |
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| Port 2 bit |
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| Port 3 bit |
• The bit latch is nothing but the one bit in the port’s SFR. It is represented as a D flip-flop.
• “Write to latch” acts as clock input for D flip-flop. The data from the internal bus is clock-in in response to a “write to latch” signal from the CPU. The Q (active low) output or Q output after inversion from D flip-flop is connected at the gate input of the drive FET.
• The On and OFF state of the drive FET due to the data available at the output of latch decides the status of the output pin.
• It is possible to read Q output of latch by activating “read latch” signal from the CPU.
• The actual port status can he read by activating “read pin” signal.
• For Port 0 and Port 2 drivers are switchable to internal ADDR/DATA and ADDR bus, respectively, by internal CONTROL signal.
• The switching is required to access external memory. During external memory accesses, the P2 SFR remains unchanged, but P0 SFR gets 1s written to it.
• Port 3 has multifunction pins. Therefore, each pin of Port 3 can be programmed to use as I/O or as one of the alternate function. This is achieved by another control input, “Alternate output function’.
• When latch bit of Port 3 contains 1, the output level is controlled by control input, “alternate output function.”
• The port pin can be configured as an input by writing 1 in the latch bit of the corresponding pin. It turns OFF the output driver FET. Then for, Ports 1,2 and 3, the pin is pulled high by the internal pull-up, but can be pulled low by an external source. There is no internal pull-up for port 0. Therefore, its output pin floats when 1 is written in the latch bit, and pin can be used as a high impedance input.
• The port 0 is said to be “true bidirectional”, because when configured as an input it floats.
• The output of Ports 1, 2 and 3 are pulled high with pull-up registers, when configured as an input. Thus they are sometimes called “quasi bidirectional” ports.
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