8085 Microprocessor Based Stepper Motor Control System

•    The motor is controlled by  ON/OFF the control winding.

•    The popular stepper motor used for demonstration in laboratories has a step size of 1.8° (i.e.,

200 steps per revolution).

•    This motor consist of four stator winding and require four switching sequence as shown.

•    The basic step size of the motor is called fult-step.

•    By altering the switching sequence, the motor can be made to run with incremental motion of half the full-step value. The switching sequence for half step rotation is shown.

Switching sequence for full step rotation

Switching sequence for half step rotation

•    A   two-phase   or   four   winding   stepper   motor   is   shown.   The   system   consist   of  8085 microprocessor  as  CPU,  EPROM  and  RAM  memory  for  program  &  data  storage  and  for stack.

8085 microprocessor based stepper motor control system

•    Using  INTEL  8279,  a  keyboard  and  six  number  of  7-segment  LED  display  have  been interfaced in the system. Through the keyboard the operator can issue commands to control the system. The LED display has been provided to display messages to the operator.

•    The windings of stepper motor are connected to the collector of Darlington pair transistors.

•    The  transistors  are  switched  ON/OFF  by  the  microprocessor  through the  ports  of8255  and buffer (74LS245).

•    A freewheeling diode is connected across each winding for fast switching.

•    The flowchart for the operational flow of the stepper motor control system is shown.

•    The  processor  has  to  output  a  switching  sequence  and  wait  for  I  to  5  mull-seconds  before sending next switching sequence. (The delay is necessary to allow the motor transients to die- out).

Flow chart for stepper motor speed control system

8085 Microprocessor Based DC Motor Speed Control System

•    Varying  the  armature  voltage  varies  the  speed  of  the  dc  motor  and  e  field  voltage  is  kept
constant.  A  controlled  rectifier  using  SCR  develops  the  required  armature  voltage  and  the uncontrolled rectifier generates the required field voltage.

•    The microprocessor controls the speed of the motor by varying the firing angle of SCRs in the controlled rectifier.

•    The system has EPROM for system program storage, and RAM for  temporary data storage and stack.

•    A keyboard has been provided to input the desired speed and other commands to operate the system.

•    In order to display the speed of the  motor, 7-segment LED display has been provided. The keyboard  and  7-segment  LED  display  has  been  interfaced  to  8085  based  system  using Keyboard display controller INTEL 8279.

8085 Microprocessor based dc motor speed control system

 
•    The speed of the dc motor is measured using a tachogenerator. It produces an analog voltage proportional to the speed of the motor.

•    Then  the  analog  signal  is  scaled  to  desired  level  by  the  signal  conditioning  circuit  and digitized  using  ADC.  (The  processor  cannot  process  the  analog  signal  directly,  hence  the analog signal is digitized using ADC).

•    The  ADC  is  interlaced  to  8085  processor  through  the  port-B  and  port-C  of  8255.  The processor  can  send  a  start  of  conversion  to  ADC  through  port-C  pin  and  at  the  end  of conversion it can read the digital data from port-B of 8255. This digital data is proportional to actual speed.

•    The processor calculates the actual speed and displays it on LEDs.

•    Also,  the  processor  compares  the  actual  speed  with  desired  speed  entered  by  the  operator through the keyboard. If there  is  a  difference  then the  error  is estimated.  The error  can  be modified  by  a  digital  control  algorithm,  (P/PI/PID/FUZZY  logic  control  algorithm)  to produce a digital control signal.

•    The digital control signal is converted to analog signal by the DAC. The analog signal is used
to alter the firing angle of SCRS in the controlled rectifiers. The operational the speed control system is shown in the following flowchart.

Flow chart for DC motor speed control system

ADC INTERFACE (APPLICATION OF 8085 MICROPROCESSOR)

In many applications, an analog device has to be interfaced to digital system. But the digital devices cannot accept the analog signals directly and so the analog signals are converted into equivalent digital signal (data) using Analog-to-Digital Converter (ADC).

The analog to digital (A/D) conversion is the reverse process of digital to analog (D/A) conversion. The A/D conversion is also called Quantization, in which the analog signal is represented binary data. The analog signals varies continuously and defined for any interval of time. The digital signals (or data) can take only finite values for discrete instant of time. If the digital data is represented by n-bit binary then it can have 2n different values. The given analog signal has to divided into steps of 2n values, and each step is represented by one of the 2n values.

The Analog to Digital Converters can be classified into two groups based on the technique involved for conversion.

The first group includes successive-approximation, counter and flash type converters. The technique involved in these devices is that the given analog signal is compared with internally generated analog signal.

The second group includes integrator converters and voltage to frequency converters. In the devices of second group, the given analog signal is converted to time or frequency and the new parameters (time or frequency) is compared with known values to produce digital signal.

The trade-off between the two techniques is based on Accuracy Vs Speed.

The successive approximation and flash type converters are accurate than the integrator and the voltage-to-frequency converters. Also, flash type is costlier. The successive-approximation type converters are used for high-speed conversion and the integrating type converters are used for high accuracy.

The resolution of the converter is the minimum analog value that can be represented by the digital data. If the ADC gives n-bit digital output and the full-scale analog input is X volts, then the resolution is 1/2n x X volts.

In ADC, another critical parameter is conversion time. The conversion time is defined as the total time required to convert an analog signal into its digital equivalent. It depends on the conversion technique and the propagation delay in various circuits.

Successive-Approximation ADC

A successive approximation ADC consist of D/A converter, successive approximation register and comparator. The figure below shows the functional blocks of a typical successive approximation A/D converter.

The conversion process is initiated by a start of conversion (SOC) signal from the processor to ADC. On receiving the SOC, the control unit of ADC will give a start command to successive approximation register and it starts generating digital signal by successive approximation method. The generated digital data is converted to analog signal by Dl A converter and then compared with given analog signal. When the analog signals are equal the comparator output informs the control unit to stop generation of digital signal. The digital data available at this instant is given as output through output register. Also the control unit generates a signal to indicate the End of Conversion (EOC) process to the processor. 

In this method the MSD (Most Significant Digit) is first set to "1" and all other digits are reset to "0". The analog signal generated for this digital data is compared with given analog signal. (Initially the comparator output will be HIGH. After comparison the output of comparator remains in HIGH state, if the given analog signal is higher than generated analog signal. Otherwise, if the given signal is less than generated signal, then the output of comparator changes from HIGH to LOW state). If the output state of comparator changes then the MSD is reset to "0" otherwise it is retained as '1'. Then the above process is repeated by setting the next higher order bit to '1'. The process is continued for each bit starting from MSD to LSD. (During a process, the higher order bits are the bits determined in earlier steps and the lower order bits are reset to "0"). After one complete cycle through MSD to LSD, the data available on the successive approximation register will be the digital equivalent of the given analog signal.

ADC interfacing to 8085 microprocessor system

The ADC can be interfaced to 8085 microprocessor system through tri-state buffer or port devices such as 8255/8155. The interfacing of ADC0801 is presented in this section. The ADC0801 is a single channel, 8-bit successive approximation type A/D converter from National Semiconductor Corporation. It is a 20-pin IC available in DIP. The pin configuration of ADC080 1 is shown in figure below.

The ADC080 I has two analog inputs V IN(+) and V IN (-) .Both the analog inputs are used for differential mode of operation. When the analog signal is single ended positive, then V IN (+) is used as input and V IN(-) is grounded. When the analog signal is single ended negative, then V IN (-) is used as input and V IN (+) is grounded. The ADC requires an external clock in the

frequency range l00 kHz to 800 kHz or the clock can be generated by connecting a RC circuit between pin 4 and 19. Typically, the clock frequency is chosen as 640 kHz to provide a conversion time of l00 sec.

A typical circuit to interface ADC0801 to 8085 processor is shown in figure below.

The ADC is connected to system bus through tri-state buffer, 74LS245. The ADC can be either memory mapped or I/O mapped in the system. The chip select signal ( CS ) is obtained from the address decoder of the 8085 system. The conversion is initiated when both CS and WR are asserted LOW.

The write control signal (WR) is used to reset the successive approximation register (SAR) of ADC and to give start of conversion (SOC). The WR of ADC can be connected directly to WR of the 8085 processor. At the falling edge of WR, the SAR is resetted and at the rising edge of WR, the conversion starts.

The end of conversion is indicated by asserting INTR LOW and this signal can be inverted to interrupt the 8085 processor. The processor reads the digital data using RD and when the data is read, the DAC will set INTR HIGH.

APPLICATIONS OF 8085 MICROPROCESSOR (DAC INTERFACE)

DAC  INTERFACE 

In many applications, the microprocessor has to produce analog signals for controlling certain analog devices. Basically the microprocessor system can produce only digital signals. In order to convert the digital signal to analog signal a Digital-to-Analog Converter. (DAC) has to be employed.

The DAC will accept a digital (binary) input and convert to analog voltage or current. Every DAC will have "n" input lines and an analog output.

The DAC require a reference analog voltage (Vref) or current (Iref) source.

The smallest possible analog value that can be represented by the n-bit binary code is called resolution. The resolution of DAC with n-bit binary input is 1/2n of reference analog value. Every analog output will be a multiple of the resolution. In some converters the input reference analog signal will be multiplied or divided by a constant to get full scale value. Now the resolution will be 1/2n of full scale value.

For example,
Consider an 8-bit DAC with reference analog voltage of 5 volts.
Now the resolution of the DAC is (1/28) x 5 volts.
The 8-bit digital input can take, 28 = 256 different values.
The analog values for all possible digital input are as shown in table below.

The maximum input digital signal will have an analog value which is equal to reference analog value minus resolution.

The digital-to-analog converters can be broadly classified into three categories, and they are

•    Current output
•    Voltage output 
•    Multiplying type

The current output DAC provides an analog current as output signal.
In voltage output DAC, the analog current signal is internally converted to voltage signal.

In multiplying type DAC, the output is given by the product of the input signal and the reference source and the product is linear over a broad range. Basically, there is not much difference between these three types and any DAC can be viewed as multiplying DAC.

Typical DAC circuit:

The basic components of a DAC are resistive network with appropriate values, switches, a reference source and a current to voltage converter as shown in figure below.

The switches in the circuit of figure above can be transistors which connects the resistance either to ground or Vref.  The resistors are connected in such a way that for any number of inputs, the total current is in binary proportion. The operational amplifier converts the current to a voltage signal V0, which can be calculated from the following equation. 

The circuit of figure shown above can be modified as 8-bitDAC, by increasing the number of R/2R ladder. For an 8-bit DAC the output voltage is given by

The time required for converting the digital signal to analog signal is called conversion time. It depends on the response time of the switching transistors and the output amplifier. If the DAC is interfaced to microprocessor then the digital data (Signal) should remain at the input of DAC, until the conversion is complete. Hence to hold the data a latch is provided at the input of DAC. 

The Digital-to-Analog converters compatible to microprocessors are available with or without internal latch and I to V converting amplifier. The AD558 of Analog Devices is an example of 8-bit DAC with an internal latch and I to V converting amplifiers. The output of AD558 is an analog voltage signal.     The AD558 can be directly interfaced to 8085 microprocessor bus and it requires only two control signals: Chip Select (CS) and Chip Enable (CE). [No handshake signals are necessary for interfacing a DAC. The time between loading two digital data to DAC is controlled by software time delay].

The DAC0808 of National Semiconductor Corporation is an example of 8-bit DAC without internal latch and I to V converting amplifier. The internal block diagram and the pin configuration of DAC0808 are shown in figure below.

The DAC0800 can be interfaced to 8085 system through an 8-bit latch as shown in figure below. The chip select (CS) signal from the decoder of the microprocessor system is delayed and inverted to clock the latch. If the DAC is memory mapped then the CS is from memory decoder. If the DAC is I/O mapped then CS is from I/O decoder. 

 

The processor sends an address, which is decoded by decoder in the microprocessor system to produce chip select signal. Then the processor sends a digital data to latch. The buffer and inverter will produce sufficient delay for CS signal so that, the latch is clocked only after the data is arrived at the input lines of the latch. When the latch is clocked the digital data is send to DAC. The DAC will produce a corresponding current signal, which is converted to voltage signal by the op-amp 741. The typical settling time of DAC0800 is 150nsec. Therefore the processor need not wait for loading next data.

INTERFACING 8259 WITH 8085 MICROPROCESSOR:

•    It requires two internal address and they are A =0 or A = 1.

•    It can be either memory mapped or I/O mapped in the system. The interfacing of 8259 to 8085 is shown in figure is I/O mapped in the system.

•    The low order data bus lines D0-D7 are connected to D0-D7 of 8259.

•    The  address  line  A0  of the  8085  processor  is  connected  to  A0   of  8259  to  provide  the  internal address.

•    The 8259 require one chip select signal. Using 3-to-8 decoder generates the chip select signal for
8259.

•    The address lines A4, A5  and A6  are used as input to decoder.

•    The control signal IO/M (low) is used as logic high enables for decoder and the address line A7  is used as logic low enable for decoder.

•    The I/O ad4ressès of 8259 are shown in table-8.5.

Working of 8259 with 8085 processor:

•    First  the  8259  should  be  programmed  by  sending  Initialization  Command  Word  (ICW)
and Operational Command Word (OCW). These command words will inform 8259 about the following,

* Type of interrupt signal (Level triggered / Edge triggered).

* Type of processor (8085/8086).

* Call address and its interval (4 or 8)

* Masking of interrupts.

* Priority of interrupts.

* Type of end of interrupts.

•    Once 8259 is programmed it is ready for accepting interrupt signal. When it receives an interrupt through any one of the interrupt lines IR0-IR7  it checks for its priority and also checks whether it
is masked or not.

•    If  the  previous  interrupt  is  completed  and  if  the  current  request  has  highest  priority  and unmasked, then it is serviced.

•    For servicing this interrupt the 8259 will send INT signal to INTR pin of 8085.

•    In response it expects an acknowledge INTA (low) from the processor.

•    When the processor accepts the interrupt, it sends three INTA (low) one by one.

•    In response to  first, second and third INTA (low) signals, the  8259 will supply CALL opcode, low byte of call address and high byte of call address respectively. Once the processor receives the call opcode and its address, it saves the content of program counter (PC) in stack and load the CALL address in PC and start executing the interrupt service routine stored in this call address.

FEATURES & FUNCTIONAL BLOCK DIAGRAM OF 8259 PROCESSOR

1. It is programmed to work with either 8085 or 8086 processor. 

2. It manage 8-interrupts according to the instructions written into its control registers.

3.  In  8086  processor,  it  supplies  the  type  number  of  the  interrupt  and  the  type  number  is programmable.  In  8085  processor,  the  interrupt  vector  address  is  programmable.  The priorities of the interrupts are programmable.

4. The interrupts can be masked or unmasked individually.

5. The 8259s can be cascaded to accept a maximum of 64 interrupts.

FUNCTIONAL BLOCK DIAGRAM OF 8259:

•    It has eight functional blocks. They are,

1.   Control logic

2.   Read Write logic

3.   Data bus buffer

4.   Interrupt Request Register (IRR)

5.   In-Service Register (ISR)

6.   Interrupt Mask Register (IMR)

7.   Priority Resolver (PR)

8.   Cascade buffer.

The data bus and its buffer are used for the following activities.

1.   The processor sends control word to data bus buffer through D0-D7.

2.   The processor read status word from data bus buffer through D0-D7.

3.  From the  data  bus  buffer  the  8259  send  type  number  (in  case  of  8086)  or  the  call opcode and    address (in case of 8085) through D0-D7 to the processor.

•    The processor uses the RD (low), WR (low) and A0 to read or write 8259.

•    The 8259 is selected by CS (low).

•    The  IRR  has  eight  input  lines  (IR0-IR7)  for  interrupts.  When  these  lines  go  high,  the request is stored in IRR. It registers a request only if the interrupt is unmasked.

•    Normally  IR0  has  highest  priority  and  IR7  has  the  lowest  priority.  The  priorities  of  the interrupt request input are also programmable.

•    First  the  8259  should  be  programmed  by  sending  Initialization  Command  Word  (ICW)
and Operational Command Word (OCW). These command words will inform 8259 about the following,

* Type of interrupt signal (Level triggered / Edge triggered).
* Type of processor (8085/8086).
* Call address and its interval (4 or 8)
* Masking of interrupts.
* Priority of interrupts.
* Type of end of interrupts.


•    The  interrupt  mask  register  (IMR)  stores  the  masking  bits  of  the  interrupt  lines  to  be masked. The relevant information is send by the processor through OCW.

•    The in-service register keeps track of which interrupt is currently being serviced.

•    The  priority  resolver  examines  the  interrupt  request,  mask  and  in-service  registers  and determines whether INT signal should be sent to the processor or not.

•    The cascade buffer/comparator is used to expand the interrupts of 8259.

•    In cascade connection one 8259 will be directly interrupting 8086 and it is called master
8259.

•    To  each  interrupt  request  input  of  master  8259  (IR0-IR7),  one  slave  8259  can  be connected. The 8259s interrupting the master 8259 are called slave 8259s.

•    Each 8259 has its own addresses so that each 8259 can be programmed independently by sending command words and independently the status bytes can be read from it.

•    The  cascade  pins  (CAS0,  CAS1   and  CAS2)  from  the  master  are  connected  to  the corresponding pins of the slave.

•    For the slave 8259, the SP (low) / EN (low) pin is tied low to let the device know that it is
a slave.

•    The SP (low) / EN (low) pin can be used as input or output signal.

•    In non-buffered mode it is used as input signal and tied to logic-I in master 8259 and logic-0 in slave 8259.

•    In buffered mode it  is used as output signal to disable the data buffers while data is transferred from 8259A to the CPU.

Cascade Connection of 8059