Interfacing Intel 8251A with 8085 Processor

The 825 1A can be either memory mapped or I/O mapped in the system.

•    8251A in I/O mapped in the system is shown in the figure.

•    Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

•    The address lines A4, A5  and A6  are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 8251A.

•    The address line A7  and the control signal IO / M(low) are used as enable for decoder.

•    The address line  A0  of 8085 is connected to  C/D(low) of 8251A to provide the internal addresses.

•    The data lines D0  – D7  are connected to D0  – D7  of the processor to achieve parallel data transfer.

•    The RESET and clock signals are supplied by the processor. Here the processor clock is directly  connected  to  8251A.  This  clock  controls  the  parallel  data  transfer  between  the processor and 8251A.

•    The output clock signal of 8085 is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

•    The TTL logic levels of the serial data lines  and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then terminated on a standard 9-pin D-.type connector.

•    In 8251A the transmission and reception baud rates can be different or same.

•    The device which requires serial communication with processor can be connected to this
9-pin D-type connector using 9-core cable.

•    The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

•    I/O addresses of 8251A interfaced to 8085 is,

USART-INTEL 8251A MICROPROCESSOR

The  8251A  is  a  programmable  serial  communication  interface  chip  designed  for synchronous and asynchronous serial data communication.It supports the serial transmission of data.It is packed in a 28 pin DIP.

Pin Diagram of 8251A

Block Diagram:

The functional block diagram of 825 1A consists five sections. They are

•    Read/Write control logic
•    Transmitter
•    Receiver
•    Data bus buffer
•    Modem control.

  The functional block diagram is,

Functional block diagram of 8251A-USART

Read/Write control logic:

•    The Read/Write Control logic interfaces the 8251A with CPU, determines the functions of the 8251A according to the control word written into its control register.

•    It monitors the data flow.

•    This  section  has  three  registers  and  they  are  control  register,  status  register  and  data buffer.

•    The active low signals RD, WR, CS and C/D(Low) are used for read/write operations with these three registers.

•    When C/D(low) is high, the control register is selected for writing control word or reading status word.

•    When C/D(low) is low, the data buffer is selected for read/write operation.

•    When the reset is high, it forces 8251A into the idle mode.

•    The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

Transmitter section:

•    The transmitter section accepts parallel data from CPU and converts them into serial data.

•    The  transmitter  section  is  double  buffered,  i.e.,  it  has  a  buffer  register  to  hold  an  8-bit parallel  data  and  another  register  called  output  register  to  convert  the  parallel  data  into
serial bits.

•    When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

•    If buffer register is empty, then TxRDY is goes to high.

•    If output register is empty then TxEMPTY goes to high.

•    The  clock  signal,  TxC  (low)  controls  the  rate  at  which  the  bits  are  transmitted  by  the
USART.

•    The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section:

•    The receiver section accepts serial data and convert them into parallel data.

•    The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

•    When the RxD line goes low, the control logic assumes it as a START bit, waits for half a
bit time and samples the line again.

•    If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

•    The CPU reads the parallel data from the buffer register.

•    When the input register loads a parallel data to buffer register, the RxRDY line goes high.

•    The clock signal RxC (low) controls the rate at which bits are received by the USART.

•    During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

•    During synchronous mode, the signal  SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

•    The MODEM control unit allows to interface  a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

•    This unit takes care of handshake signals for MODEM interface.

KEYBOARD AND DISPLAY INTERFACE USING INTEL 8279 MICROPROCESSOR

In a microprocessor b   system,   when   keyboard   and   7-segment   LED   display   is interfaced using ports or latches then the processor has to carry the following task.

• Keyboard scanning
• Key debouncing
• Key code generation
• Sending display code to LED
• Display refreshing

Interfacing 8279 with 8085 processor:

 •    A  typical  Hexa  keyboard  and  7-segment  LED  display  interfacing  circuit  using  8279  is shown.

•    The  circuit  can  be  used  in  8085  microprocessor  system  and  consist  of  16  numbers  of hexa-keys and 6 numbers of 7-segment LEDs.

•    The 7-segment LEDs can be used to display six digit alphanumeric character.

•    The 8279 can be either memory mapped or I/O mapped in the system. In the circuit shown
is the 8279 is I/O mapped.

•    The address line A0 of the system is used as A0 of 8279.

•    The clock signal for  8279 is obtained by dividing the output clock signal of  8085 by  a clock divider circuit.

•    The chip select signal is obtained from the I/O address decoder of the 8085 system. The chip select signals for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A4, A5 and A6 are used as input to decoder.

•    The address line A7 and the control signal IO/M (low) are used as enable for decoder.

•    The chip select signal IOCS-3 is used to select 8279.

•    The I/O address of the internal devices of 8279 are shown in table.

•    The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in encoded  scan.  (Because  in  decoded  scan,  only  4  numbers  of  7-segment  LEDs  can  be interfaced):

•    In encoded scan the output of scan lines will be binary count. Therefore an external, 3-to-
8 decoder is used to decode the scan lines SL0, SL1  and SL2  of 8279 to produce eight scan lines S0 to S7.

•    The decoded scan lines S0 and S1  are common for keyboard and display.

•    The decoded scan lines S2  to S5  are used only for display and the decoded scan lines S6
and S7 are not used in the system.

•    Anode and Cathode drivers are provided to take care of the current requirement of LEDs.

•    The pnp transistors, BC 158 are used as driver transistors.

•    The anode drivers are called segment drivers and cathode drivers are called digit drivers.

•    The 8279 output the display code for one digit through its output lines (OUT A0  to OUT
A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

•    The display code is inverted by segment drivers and sent to segment bus.

•    The  scan  code  is  decoded  by  the  decoder  and  turns  ON  the  corresponding digit  driver. Now  one  digit  of  the  display  character  is  displayed.  After  a  small  interval  (10  milli- second, typical), the display is turned OFF (i.e., display is blanked) and the above process
is repeated for next digit. Thus multiplexed display is performed by 8279.

•    The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as columns and decoded scan lines S0 and S1 as rows.

•    A hexa key is placed at the crossing point of each row and column. A key press will short the row and column. Normally the column and row line will be high.

•    During scanning the 8279 will output binary  count on SL0  to SL3, which is decoded  by decoder to make a row as zero. When a row is zero the 8279 reads the columns. If there is
a key press then the corresponding column will be zero.

•    If 8279 detects a key press then it wait for debounce time and again read the columns to generate key code.

•    In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key press. The keycode consist of the binary value of the column and row in which the key is found and the status of shift and control key.

•    After a scan time, the next row is made zero and the above process is repeated and so on. Thus 8279 continuously scan the keyboard.

Interfacing 8279 with 8086 processor:

• A  typical  Hexa  keyboard  and  7-segment  LED  display  interfacing  circuit  using  8279  f
8086 based system is shown.

•        The system consists of 16 numbers of hexa-keys and numbers of 7-segment LEDs. The 7- segment LEDs can be used to display eight-digit alphanumeric character.

•    The 8279 can be either memory mapped or I/O mapped in the system. In the circuit shown
is I/O mapped.

•    The address line A1 of the system is used as A0 of 8279.

•    The clock signal for 8279 is obtained by dividing the PCLK (peripheral clock) of 8284 by
a clock divider circuit.

•    The chip select signals, for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A5, A6 and A7 are used as input to decoder.

•    The address line A0  and the control signal M  /IO (low) are used as enable for decoder. The chip select signal IOCS-3 is used to select 8279.

•    The I/O address of the internal devices of 8279 is shown in table.

•    The circuit has 6 numbers of 7-segment LEDs and so the 8279 has to be programmed in encoded  scan.  (Because  in  decoded  scan,  only  4  numbers  of  7-segment  LEDs  can  be interfaced):

•    In encoded scan the output of scan lines will be binary count. Therefore an external, 3-to-
8 decoder is used to decode the scan lines SL0, SL1  and SL2  of 8279 to produce eight scan lines S0 to S7.

•    The decoded scan lines S0 and S1  are common for keyboard and display.

•    The decoded scan lines S2  to S5  are used only for display and the decoded scan lines S6
and S7 are not used in the system.

•    Anode and Cathode drivers are provided to take care of the current requirement of LEDs.

•    The pnp transistors, BC 158 are used as driver transistors.

•    The anode drivers are called segment drivers and cathode drivers are called digit drivers.

•    The 8279 output the display code for one digit through its output lines (OUT A0  to OUT
A3 and OUT B0 to OUT B3) and send a scan code through, SL0- SL3.

•    The display code is inverted by segment drivers and sent to segment bus.

•    The  scan  code  is  decoded  by  the  decoder  and  turns  ON  the  corresponding digit  driver. Now  one  digit  of  the  display  character  is  displayed.  After  a  small  interval  (10  milli-
second, typical), the display is turned OFF (i.e., display is blanked) and the above process
is repeated for next digit. Thus multiplexed display is performed by 8279.

•    The keyboard matrix is- formed using the return lines, RL0 to RL3 of 8279 as columns and decoded scan lines S0 and S1 as rows.

•    A hexa key is placed at the crossing point of each row and column. A key press will short the row and column. Normally the column and row line will be high.

•    During scanning the 8279 will output binary  count on SL0  to SL3, which is decoded  by decoder to make a row as zero. When a row is zero the 8279 reads the columns. If there is
a key press then the corresponding column will be zero.

•    If 8279 detects a key press then it wait for debounce time and again read the columns to generate key code.

•    In encoded scan keyboard mode, the 8279 stores an 8-bit code for each valid key press. The keycode consist of the binary value of the column and row in which the key is found
and the status of shift and control key.

•    After a scan time, the next row is made zero and the above process is repeated and so on. Thus 8279 continuously scan the keyboard.

INTEL 8279 MICROPROCESSOR - KEYBOARD/DISPLAY CONTROLLER

The INTEL 8279 is specially developed for interfacing keyboard and display devices
to 8085/8086/8088 microprocessor based system. The important features of 8279 are,

• Simultaneous keyboard and display operations.
• Scanned keyboard mode.
• Scanned sensor mode.
• 8-character keyboard FIFO.
• 1 6-character display.
• Right or left entry 1 6-byte display RAM.
• Programmable scan timing.

Block diagram of 8279:

•    The functional block diagram of 8279 is shown.

•    The four major sections of 8279 are keyboard, scan, display and CPU interface.

Keyboard section:

•    The keyboard section consists of eight return lines RL0 – RL7 that can be used to form the columns of a keyboard matrix.

•    It   has   two   additional   input   :   shift   and   control/strobe.   The   keys   are   automatically debounced.

•    The two operating modes of keyboard section are 2-key lockout and N-key rollover.

•    In the 2-key lockout mode, if two keys are pressed simultaneously, only the first key is recognized.

•    In the N-key rollover mode simultaneous keys are recognized and their codes are stored in
FIFO.

•    The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM.

•    The FIFO can store eight key codes in the scan keyboard mode. The status of the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,

•    In sensor  matrix mode the condition (i.e., open/close status) of 64  switches is stored in FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor.

Display section:

•    The display section has eight output lines divided into two groups A0-A3 and B0-B3.

•    The output lines can be used either as a single group of eight lines or as two  groups of four lines, in conjunction with the scan lines for a multiplexed display.

•    The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs.

•    The cathodes are connected to scan lines through driver transistors.

•    The display can be blanked by BD (low) line.

•    The display section consists of 16 x 8 display RAM. The CPU can read from or write into any location of the display RAM.

Scan section:

•    The scan section has a scan counter and four scan lines, SL0 to SL3.

•    In decoded scan mode, the output of scan lines will be similar to a 2-to-4 decoder.

•    In encoded scan mode, the output of scan lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output.

•    The scan lines are common for keyboard and display.

•    The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a multiplexed display, to turn ON/OFF.

CPU interface section:

•    The CPU interface section takes care of data transfer between 8279 and the processor.

•    This section has eight bidirectional data lines DB0  to DB7  for data transfer between 8279
and CPU.

•    It  requires  two  internal  address  A  =0  for  selecting  data  buffer  and  A  =  1  for  selecting control register of8279.

•    The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.

•    It has an interrupt request line IRQ, for interrupt driven data transfer with processor.

•    The  8279  require  an  internal  clock  frequency  of  100  kHz.  This  can  be  obtained  by dividing the input clock by an internal prescaler.

•    The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.

Programming the 8279:

•    The  8279  can  be  programmed  to  perform  various  functions  through  eight  command words.