Interfacing of 8257 with 8085 processor

•    A simple schematic for interfacing the 8257 with 8085 processor is shown.

•    The 8257 can be either memory mapped or I/O mapped in the system.

•    In the schematic shown in figure is I/O mapped in the system.

•    Using a 3-to-8 decoder generates the chip select signals for I/O mapped devices.

•    The address lines A4, A5 and A6 are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this the chip select signal IOCS-6 is used to select 8257.

•    The address line A7 and the control signal IO/M (low) are used as enable for decoder.

•    The  D0-D7  lines  of  8257  are  connected  to  data  bus  lines  D0-D7  for  data  transfer  with processor during programming mode.

•    These lines (D0-D7) are also used by 8257 to supply the memory address A8-A15  during
the DMA mode.

•    The 8257 also supply two control signals ADSTB and AEN to latch the address supplied
by it during DMA mode on external latches.

•    Two  8-bit  latches  are  provided  to  hold  the  16-bit  memory  address  during  DMA  mode. During DMA mode, the AEN signal is also used to disable the buffers and latches used
for address, data and control signals of the processor.

•    The  8257  provide  separate  read  and  write  control  signals  for  memory  and  I/O  devices during DMA.

•    Therefore the RD (low), WR (low) and IO/M (low) of the 8085 processor are decoded by
a suitable logic circuit to generate separate read and write control signals f memory and
I/O devices.

•    The output clock of 8085 processor should be inverted and supplied to 8257 clock input for proper operation.

•    The HRQ output of 8257 is connected to HOLD input of 8085 in order to make a HOLD
request to the processor.

•    The HLDA output of 8085 is connected to HLDA input of 8257, in order to receive the acknowledge signal from the processor once the HOLD request is accepted.

•    The RESET OUT of 8085 processor is connected to RESET of 8257.

•    The I/O addresses of the internal registers of 8257 are listed in table.

PROGRAMMABLE DMA CONTROLLER - INTEL 8257:

•    It is a device to transfer the data directly between IO device and memory without through
the CPU. So it performs a high-speed data transfer between memory and I/O device.
•    The features of 8257 is,

1.   The 8257 has four channels and so it can be used to provide DMA to four I/O
devices
2.   Each channel can be independently programmable to transfer up to 64kb of data
by DMA.
3.   Each  channel  can  be  independently  perform  read  transfer,  write  transfer  and verify transfer.

•    It is a 40 pin IC and the pin diagram is,

Functional Block Diagram of 8257:

•    The functional block diagram of 8257 is shown in fig.
•    The  functional  blocks  of  8257  are  data  bus  buffer,  read/write  logic,  control  logic, priority resolver and four numbers of DMA channels.
•    Each  channel  has  two  programmable  16-bit  registers  named  as  address  register  and count register.

•    Address register is used to store the starting address of memory location for DMA data transfer.
•    The    address    in    the    address    register    is    automatically    incremented    after    every read/write/verify transfer.
•    The count register is used to count the number of byte or word transferred by DMA
•    The format of count register is,

•    14-bits B0-B13  is used to  count value and  a 2-bits is used for indicate the type of DMA
transfer (Read/Write/Veri1 transfer).
•    In read transfer the data is transferred from memory to I/O device.
•    In write transfer the data is transferred from I/O device to memory.
•    Verification   operations   generate   the   DMA   addresses   without   generating   the   DMA
memory and I/O control signals.
•    The 8257 has two eight bit registers called mode set register and status register.
•    The format of mode set register is,

•    The use of mode set register is,

1.   Enable/disable a channel.
2.   Fixed/rotating priority
3.   Stop DMA on terminal count.
4.   Extended/normal write time.
5.   Auto reloading of channel-2.

•    The bits B0, B1, B2, and B3 of mode set register are used to enable/disable channel -0, 1, 2
and 3 respectively. A one in these bit position will enable a particular channel and a zero
will disable it
•    If the bit B4 is set to one, then the channels will have rotating priority and if it zero then the channels wilt have fixed priority.

1.  In rotating priority after servicing a channel its priority is made as lowest.
2.  In fixed priority the channel-0 has highest priority and channel-2 has lowest priority.

•    If the bit B5  is set to one, then the timing of low write signals (MEMW and IOW) will be extended.
•    If the bit B6 is set to one then the DMA operation is stopped at the terminal count.
•    The bit B7 is used to select the auto load feature for DMA channel-2.
•    When bit B7  is set to one, then the content of channel-3 count and address registers are loaded  in  channel-2  count  and  address  registers  respectively  whenever  the  channel-2
reaches terminal count. When this mode is activated the number of channels available for
DMA reduces from four to three.
•    The format of status register of 8257 is shown in fig.

•    The  bit  B0,  B1,  B2,  and  B3  of  status  register  indicates  the  terminal  count  status  of channel-0, 1,2 and 3 respectively. A one in these bit positions indicates that the particular
channel has reached terminal count.
•    These status bits are cleared after a read operation by microprocessor.
•    The bit B4  of status register is called update flag and a one in this bit position indicates that  the  channel-2  register  has  been  reloaded  from  channel-3  registers  in  the  auto  load mode of operation.
•    The internal addresses of the registers of 8257 are listed in table.

Interfacing 8251A to 8086 Processor

•    The chip select for I/O mapped devices are generated by using a 3-to-8 decoder.

•    The address lines A5, A6  and A7 are decoded to generate eight chip select signals (IOCS-0
to IOCS-7) and in this, the chip select signal IOCS-2 is used to select 825lA.

•    The address line A0 and the control signal M/IO(low) are used as enable for decoder.

•    The line A1 of 8086 is connected to C/D(low) of 8251A to provide the internal addresses.

•    The lines D0 – D7 connected to D0 – D7 of the processor to achieve parallel data transfer.

•    The RESET and clock signals are supplied by 8284 clock generator. Here the processor clock  is  directly  connected  to  8251A.  This  clock  controls  the  parallel  data  transfer
between the processor and 825lA.

•    8251A in I/O mapped in the system is shown in the figure.

•    The peripheral clock (PCLK) supplied by 8284, is divided by suitable clock dividers like programmable timer 8254 and then used as clock for serial transmission and reception.

•    In 8251A the transmission and reception baud rates can be different or same.

•    The TTL logic levels of the serial data lines  and the control signals necessary for serial transmission and reception are converted to RS232 logic levels using MAX232 and then
terminated on a standard 9-pin D-.type connector.

•    The device, which requires serial communication with processor, can be connected to this
9-pin D-type connector using 9-core cable.

•    The signals TxEMPTY, TxRDY and RxRDY can be used as interrupt signals to initiate interrupt driven data transfer scheme between processor and 8251 A.

 •    The I/O addresses allotted to the internal devices of 8251A are listed in table.